Principal Cache RTL Design - CPU Team

AMD
Bengaluru
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: mastersSkills: ["Leadership","Communication","Teamwork","Problem-solving","Documentation"]

Lead RTL design and integration for high-performance x86-core ISA features, including clock/reset/power management, cache coherency, and cross-IP integration. Mentor a design team across multi-site environments, collaborate with DFT, Physical Design, and SOC teams, and drive design quality through verification and linting.

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FursaFursa
AMD
AMD
3 months ago

Principal Cache RTL Design - CPU Team

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead RTL design and integration for high-performance x86-core ISA features, including clock/reset/power management, cache coherency, and cross-IP integration. Mentor a design team across multi-site environments, collaborate with DFT, Physical Design, and SOC teams, and drive design quality through verification and linting.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •RTL design of high-performance x86-core ISA features, clock/reset/power features of processor, IP integration, sub-system level design
  • •Architect and design power management features, cache, coherency
  • •Design optimization for power-efficient IP using low-power techniques
  • •Inter-IP integration issue resolution and ownership of Clock-Domain Crossing and linting aspects
  • •Lead design team across RTL deliverables and mentor junior RTL engineers

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •15+ years of experience in Digital IP/ASIC design and Verilog RTL development
  • •Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
  • •Proficient in RTL design verification, design quality checks, synthesis, timing closure and post-silicon validation
  • •Expert on Verilog RTL design with experience on multiscale digital IP/ASIC projects
  • •Proficiency with front-end EDA tools and scripting languages (Python or Perl) is a plus
Experience:15+ yearsSemiconductorASICIP design
Education:Master's in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering
Skills:LeadershipCommunicationTeamworkProblem-solvingDocumentation
Languages:English
Tech Stack:VerilogRTLPythonPerlEDA toolsDFTSynthesisTiming closurePost-silicon validation

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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