Physical Design / Implementation Lead

Neurophos
Austin, San Jose
Workplace: OnsiteFull timeUSD 225,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Team leadership","Process automation","Cross-functional collaboration","Technical ownership","Optimization"]

Own the end-to-end SoC physical design and implementation process, guiding designs from RTL through tapeout on leading-edge process nodes. Lead and grow a multi-site team delivering optimized GDSII for subsystem and SoC levels, driving synthesis-flow and timing-closure automation, and designing power and clock distribution networks. Partner closely with RTL/DV and analog teams to integrate mixed-signal into the digital flow while managing physical verification and IP/library assets.

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Neurophos
Neurophos
2 days ago

Physical Design / Implementation Lead

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Job Summary

Own the end-to-end SoC physical design and implementation process, guiding designs from RTL through tapeout on leading-edge process nodes. Lead and grow a multi-site team delivering optimized GDSII for subsystem and SoC levels, driving synthesis-flow and timing-closure automation, and designing power and clock distribution networks. Partner closely with RTL/DV and analog teams to integrate mixed-signal into the digital flow while managing physical verification and IP/library assets.
Location: Austin, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Own physical design and implementation end-to-end from synthesis through tapeout on leading-edge process nodes (TSMC N3 strongly preferred; deep FinFET 7nm–3nm required).
  • •Optimize and automate synthesis flow and lead intake of new process technologies for upcoming nodes.
  • •Optimize and automate timing closure at the block and subsystem level.
  • •Design and optimize power and clock architecture distribution networks.
  • •Build and lead the physical design team (hire, ramp, and manage engineers) and coordinate flow/schedule decisions with RTL/DV and analog teams.

Pay and Benefits

Salary: USD 225,000 - 300,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceHsa ContributionsPaid Leave401kEquityDentalVisionLife InsuranceCritical IllnessAccident InsuranceVoluntary Benefits

Key Requirements

  • •Lead physical design/implementation through tapeout on large, complex SoCs, owning synthesis, timing closure, power, and physical verification at a senior level.
  • •Hands-on experience on advanced process nodes; TSMC N3 strongly preferred and FinFET-class (7nm–3nm) experience required.
  • •Deep power and clock design experience at scale, ideally from CPU-class or very large SoC work.
  • •Track record leading and growing a team.
  • •Experience integrating analog/mixed-signal blocks into a digital implementation flow (preferred).
Experience:SoCSemiconductorsHardwareAI compute
Skills:Team leadershipProcess automationCross-functional collaborationTechnical ownershipOptimization
Tech Stack:GDSIICadenceRTLSynthesisTiming closurePower and clock distributionTSMC N3FinFETGAA

Company Brief

Neurophos
Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Growth Stage Startup
Funding: Series A
Headquarters: Austin, United States
Founded: 2020
WebsiteLinkedIn