Sort Interface Pathfinding and Development Engineer

Intel
United States
Workplace: OnsiteFull timeUSD 133,800 - 255,200 annuallyFunction: Product ManagementExperience: 6+ yearsEducation: bachelorsSkills: ["Collaborative mindset","Communication","Analytical thinking","Self-starter","Continuous learning"]

Build and qualify next-generation probing technologies for wafer and die sort operations within Intel’s Advanced Packaging, Test and Manufacturing organization. Lead electro-mechanical pathfinding and test hardware development, partner with Foundry and OSAT customers to translate chiplet/package needs into scalable interface specifications, and author interface design rules and kits (IDKs). Collaborate across DFT teams, vendors, and PCB suppliers to drive supplier accountability and manufacturing readiness for NPI.

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Intel
Intel
3 days ago

Sort Interface Pathfinding and Development Engineer

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Job Summary

Build and qualify next-generation probing technologies for wafer and die sort operations within Intel’s Advanced Packaging, Test and Manufacturing organization. Lead electro-mechanical pathfinding and test hardware development, partner with Foundry and OSAT customers to translate chiplet/package needs into scalable interface specifications, and author interface design rules and kits (IDKs). Collaborate across DFT teams, vendors, and PCB suppliers to drive supplier accountability and manufacturing readiness for NPI.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Product Management
Seniority: Mid level

Key Responsibilities

  • •Formulate and execute DOE to optimize and qualify next-generation probing technologies and contact architectures for wafer and die sort operations.
  • •Serve as the lead technical liaison for Foundry and OSAT customers, translating chiplet and package requirements into scalable sort interface specifications.
  • •Author industry-standard sort design rules and Interface Design Kits (IDKs) to streamline ecosystem integration for external fabless customers and design partners.
  • •Collaborate with customer design and DFT teams to architect test interface hardware, resolve technical gaps, and align testability roadmaps.
  • •Partner with test solution vendors and PCB suppliers, directing supplier and pathfinding initiatives to support on-time NPI hardware delivery readiness.

Pay and Benefits

Salary: USD 133,800 - 255,200 annually
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •Bachelor’s degree (or Master’s/PhD) in electrical, mechanical, materials science, or related STEM with 6+ / 4+ / 2+ years industry experience.
  • •Experience with wafer/die sort technology, prober-tester cell integration, and qualification of advanced probe card technologies.
  • •Ability to structure and execute Design of Experiments (DOE) to evaluate probing margins, yield, and process health.
  • •Direct experience in ATE test hardware/methodology, sort/class product development, or PCB/space transformer/substrate design rules and stackup architectures.
  • •(Preferred) Experience with advanced probing process characterization, OSAT/Foundry test operations, or fine-pitch micro-bumps and 2.5D/3D architectures; hands-on ATE platform experience (e.g., Advantest V93k, Teradyne Ultra-FLEX).
Experience:6+ yearsSemiconductorsAdvanced packagingATE testOSATFoundryWafer sort
Education:Bachelor's in Electrical Engineering, Mechanical Engineering, Materials Science, or related STEM
Skills:Collaborative mindsetCommunicationAnalytical thinkingSelf-starterContinuous learning
Tech Stack:Design of Experiments (DOE)Probing technologiesProbe cardElectro-mechanical pathfindingATE test hardwarePCBInterface Design Kits (IDKs)EMIBEMIB-TFoverosFoveros DirectAdvantest V93kTeradyne Ultra-FLEX2.5D3DMicro-bumpsDFTOSATFoundry test operations

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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