SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O
AMD
Santa Clara
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["SystemVerilog","Verilog","VCS","Perl","Python","Shell scripting","SerDes","Ethernet"]Contribute to ASIC design for high-performance network chips (AINIC and DPU) as part of the NTSG ASIC Design Team. Lead front-end RTL design and integration of Ethernet subsystems, collaborate across architecture, IP, and PD teams to achieve first-pass silicon, and support post-silicon yield learning from Santa Clara, CA.
