Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

Cisco
San Jose
Workplace: HybridFull timeUSD 152,500 - 219,200 annuallyFunction: Energy & Utilities OperationsExperience: 4+ yearsEducation: bachelorsSkills: ["Communication","Collaboration"]

Design, verify, and validate next-generation ASIC packaging by developing and implementing ultra-high-speed signal and power integrity design rules. Perform pre- and post-layout SI/PI analysis across interposer, substrate, and PCB, then collaborate with layout teams, system partners, and vendors to resolve complex SI/PI issues. Contribute to package design and release through extraction and reporting, supporting high-volume, high-quality ASIC deployments.

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FursaFursa
Cisco
Cisco
3 months ago

Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Design, verify, and validate next-generation ASIC packaging by developing and implementing ultra-high-speed signal and power integrity design rules. Perform pre- and post-layout SI/PI analysis across interposer, substrate, and PCB, then collaborate with layout teams, system partners, and vendors to resolve complex SI/PI issues. Contribute to package design and release through extraction and reporting, supporting high-volume, high-quality ASIC deployments.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Energy & Utilities Operations
Seniority: Mid level

Key Responsibilities

  • •Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
  • •Analyze substrate signal integrity and power integrity, and collaborate with the layout team to optimize solutions across interposer, substrate, and PCB.
  • •Design, document, and develop ASIC packages, including post-layout extraction and reporting for high-volume, high-quality releases.
  • •Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues.
  • •Support advanced IC package design and heterogeneous system integration for next-generation ASIC packaging across Cisco platforms.

Pay and Benefits

Salary: USD 152,500 - 219,200 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalDisability InsuranceLife InsurancePaid HolidaysPaid Leave

Key Requirements

  • •Bachelor's degree in Electrical Engineering and 4+ years of signal and power integrity experience, or equivalent (Master's with 2+ years, or PhD with 0+ years).
  • •Expertise in high-speed design principles including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis for 56G PAM4 SerDes architectures.
  • •Experience with pre- and post-layout SI/PI simulations using tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • •Experience with detailed layout reviews and physical validation using Cadence APD and Ansys EM flows, including crosstalk mitigation.
  • •Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation.
Experience:4+ years
Education:Bachelor's in Electrical Engineering
Skills:CommunicationCollaboration
Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EMSPICEVector Network AnalysisIBISUCIeCoWoSEMIB

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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