Cisco

1 month ago

Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Seeking a Signal and Power Integrity Engineer to develop and verify high‑performance ASIC packaging. You’ll analyze SI/PI across interposer, substrate, and PCB, design ASIC packages for high-volume production, and collaborate with system partners to resolve complex issues using advanced design rules in a hybrid environment near San Jose.

Location: San Jose

Workplace: Hybrid

Employment Type: Full time

Job Function: Energy & Utilities Operations

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
•Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
•Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
•Work with cross-functional teams to deploy packaging solutions across Cisco platforms and continuously improve SI/PI performance.

Pay and Benefits

Perks:Health Insurance401kPaid LeaveSick TimeRsus

Key Requirements

•Bachelor's degree in Electrical Engineering with 4+ years of signal and power integrity experience, or Master's degree with 2+ years, or PhD with 0+ years, or equivalent related work experience.
•High-Speed Architecture & Theory: Expertise in high-speed design principles (56G PAM4 SerDes, channel modeling, BER prediction).
•SI/PI Simulation Proficiency: Experience with pre- and post-layout simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
•Layout Review & Physical Validation: Experience with Cadence APD and Ansys EM flows for layout reviews and crosstalk mitigation.
•Circuit Analysis: Working knowledge of SPICE for circuit-level analysis and performance validation.

Experience:SemiconductorASICHardwareNetworks

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingPresentationAnalytical thinking

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICE

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

1 month ago

Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Hybrid

Employment Type: Full time

Job Function: Energy & Utilities Operations

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
•Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
•Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
•Work with cross-functional teams to deploy packaging solutions across Cisco platforms and continuously improve SI/PI performance.

Pay and Benefits

Perks:Health Insurance401kPaid LeaveSick TimeRsus

Key Requirements

•Bachelor's degree in Electrical Engineering with 4+ years of signal and power integrity experience, or Master's degree with 2+ years, or PhD with 0+ years, or equivalent related work experience.
•High-Speed Architecture & Theory: Expertise in high-speed design principles (56G PAM4 SerDes, channel modeling, BER prediction).
•SI/PI Simulation Proficiency: Experience with pre- and post-layout simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
•Layout Review & Physical Validation: Experience with Cadence APD and Ansys EM flows for layout reviews and crosstalk mitigation.
•Circuit Analysis: Working knowledge of SPICE for circuit-level analysis and performance validation.

Experience:SemiconductorASICHardwareNetworks

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingPresentationAnalytical thinking

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICE

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor