ASIC Engineer || Physical Design | Floor Planning | GSP & PD | Exp - 8 to 11 years

Cisco
Bengaluru, Hyderabad
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-11 yearsEducation: mastersSkills: ["Debugging","Problem-solving","Creative solutions","Process reviews","Methodology development"]

Join the Cisco SiliconOne Physical Design team in Bangalore to help craft next-generation networking ASICs. You’ll drive the RTL-to-GDS implementation flow—hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks—while optimizing performance and die size. You’ll also develop automation within STA tools, enable methodology improvements, and review multi-mode/multi-corner designs for sign-off.

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FursaFursa
Cisco
Cisco
1 week ago

ASIC Engineer || Physical Design | Floor Planning | GSP & PD | Exp - 8 to 11 years

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Job Summary

Join the Cisco SiliconOne Physical Design team in Bangalore to help craft next-generation networking ASICs. You’ll drive the RTL-to-GDS implementation flow—hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks—while optimizing performance and die size. You’ll also develop automation within STA tools, enable methodology improvements, and review multi-mode/multi-corner designs for sign-off.
Location: Bengaluru, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive the backend RTL-to-GDS implementation flow for next-generation networking ASICs, including hierarchical floor planning, place & route, and timing closure.
  • •Perform power integrity analysis and ensure reliable results through static timing verification, physical verification, and equivalence checks.
  • •Set up and run STA convergence methodology, including reviews and sign-off for multi-mode, multi-corner designs.
  • •Develop automation scripts within STA tools to improve methodology and streamline physical design work.
  • •Support performance and die size optimization by enabling timing ECO strategy development and convergence (including Tweaker/Primetime-based ECO flows).

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering with 8+ years of experience.
  • •Hands-on ASIC physical implementation across floor planning, clock/power distribution, global signal planning, I/O planning, and hard IP integration.
  • •Hierarchical design implementation, including timing closure, physical convergence, and related verification/equivalence checks.
  • •Power integrity analysis and STA setup/convergence methodology, including reviews and sign-off for multi-mode, multi-corner designs.
  • •Experience with large designs (>100M gates) using advanced sub 16/14/7/5/3nm process technologies.
Experience:8-11 years
Education:Master's in Electrical or Computer Engineering
Skills:DebuggingProblem-solvingCreative solutionsProcess reviewsMethodology development
Tech Stack:RTLGDSFloor planningPlace & routeTiming closurePower integrityStatic timing verificationSTAMulti-modeMulti-cornerPhysical verificationEquivalence checksGlobal signal planningI/O planningHard IP integrationHierarchical designCTSTweakerPrimetimeSub 16/14/7/5/3nm

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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