Principal Product Engineer – High-Speed IP Memory

Cadence Design Systems
Seoul, Dominican Republic
Full timeFunction: Communications, PR & CommunityExperience: 7+ yearsSkills: ["Complex problem-solving","Root cause analysis","Technical leadership","Communication","Ownership"]

Own the product engineering lifecycle for high-performance memory subsystem IP, from pre-sales engagement through pre-silicon integration and post-silicon bring-up. Serve as the primary customer interface for complex DDR/LPDDR/GDDR/HBM integration, leading technical discussions, SoC reviews, RTL and gate-level simulation, and timing closure strategies. Drive integration methodology improvements, mentor engineers, collaborate with R&D/validation/apps, and use AI tools to accelerate debug and decision-making.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Principal Product Engineer – High-Speed IP Memory

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 hours agoStatus: Live

Job Summary

Own the product engineering lifecycle for high-performance memory subsystem IP, from pre-sales engagement through pre-silicon integration and post-silicon bring-up. Serve as the primary customer interface for complex DDR/LPDDR/GDDR/HBM integration, leading technical discussions, SoC reviews, RTL and gate-level simulation, and timing closure strategies. Drive integration methodology improvements, mentor engineers, collaborate with R&D/validation/apps, and use AI tools to accelerate debug and decision-making.
Location: Seoul, Dominican Republic
Employment Type: Full time
Job Function: Communications, PR & Community

Key Responsibilities

  • •Act as primary product engineering owner for memory subsystems (DDR, LPDDR, GDDR, HBM, etc) at the customer level.
  • •Lead customer engagements, drive technical discussions, design reviews, and deployment strategy.
  • •Own and drive resolution of complex subsystem integration and implementation issues, including PHY/controller SoC integration reviews.
  • •Provide technical leadership for RTL, gate-level simulations, and timing closure strategies.
  • •Lead post-silicon bring-up and debug activities and mentor junior engineers while collaborating with R&D, validation, and applications teams.

Key Requirements

  • •Bachelor’s in electrical engineering, Computer Engineering, or related field with 7+ years of experience, or Master’s with 5+ years, or PhD with relevant experience.
  • •Strong experience with high-speed interface IP and deep understanding of RTL design, gate-level verification, and simulation methodologies.
  • •Experience with synthesis, STA, and timing closure; backend knowledge is a plus.
  • •Familiarity with DFT methodologies, test flows, and system validation approaches.
  • •Proven ability to solve complex technical problems and drive root cause to closure, including leading cross-functional technical efforts.
Experience:7+ years
Skills:Complex problem-solvingRoot cause analysisTechnical leadershipCommunicationOwnership
Tech Stack:RTLGate-level verificationSimulationSynthesisSTATiming closureDFTTest flowsSystem validationAI toolsData analysis

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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