Lead Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","VHDL","HVL","UVM","Assertions","Constraint Randomization","Functional Coverage","Code Coverage","RTL","GLS","Debug","Gate-level Simulations","Power-aware RTL","Formal Verification","Analog models"]

Lead Design Engineer responsible for enhancing and building functional verification environments for digital IP, coordinating with RTL, physical, analog and modelling teams, and driving verification methodologies to meet DV metrics across customer configurations on Cadence’s multi-domain platforms. You will mentor a small team, implement Verilog HVL with UVM, and contribute to assertions, coverage and gate-level simulations.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
6 months ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Lead Design Engineer responsible for enhancing and building functional verification environments for digital IP, coordinating with RTL, physical, analog and modelling teams, and driving verification methodologies to meet DV metrics across customer configurations on Cadence’s multi-domain platforms. You will mentor a small team, implement Verilog HVL with UVM, and contribute to assertions, coverage and gate-level simulations.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Work with the existing functional verification environment, add new features or create a new verification environment from scratch and ensure customer configurations meet DV metrics; may support customers with design issues.
  • •Participate in technical alignment with verification experts to define verification strategy and architect verification environments; interface with RTL, physical design, analog design and modelling teams.
  • •Contribute towards defining, developing and deploying new functional verification methodologies.
  • •Ensure engineers have strong background in verification fundamentals, environment planning & development, and test plan creation.
  • •Demonstrate prior digital verification experience in multi-protocol PHY IPs (SerDes, USB/DPHY,UCIe).

Key Requirements

  • •5+ years experience with BE/B.Tech or M.E/M.Tech
  • •strong background in functional verification fundamentals, verification environment planning & development, test plan creation
  • •Prior digital verification experience in serial bus multiprotocol PHY IPs (such as SerDes, USB/DPHY,UCIe) is expected
  • •Strong expertise in Verilog, HVL (SV, e) with UVM methodology
  • •Experience in assertions development/closure, constraint randomization, functional coverage, code coverage
Experience:5+ yearsSemiconductorsElectronicsEDAASIC
Education:Bachelor's
Skills:VerilogVHDLHVLUVMAssertionsConstraint RandomizationFunctional CoverageCode CoverageRTLGLSDebugGate-level SimulationsPower-aware RTLFormal VerificationAnalog models
Languages:English
Tech Stack:VerilogHVLSVEUVMRTLGLSAssertionsConstraint randomizationFunctional coverageCode coverageGate-level simulationsAnalog models

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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