Lead Design Engineer
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","VHDL","HVL","UVM","Assertions","Constraint Randomization","Functional Coverage","Code Coverage","RTL","GLS","Debug","Gate-level Simulations","Power-aware RTL","Formal Verification","Analog models"]Lead Design Engineer responsible for enhancing and building functional verification environments for digital IP, coordinating with RTL, physical, analog and modelling teams, and driving verification methodologies to meet DV metrics across customer configurations on Cadence’s multi-domain platforms. You will mentor a small team, implement Verilog HVL with UVM, and contribute to assertions, coverage and gate-level simulations.
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