Sr Principal Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 154,000 - 286,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Communication","Interpersonal skills","Debugging"]

Shape the future of system-level chip design verification in a North America hardware emulation and FPGA prototyping customer-facing role. You’ll collaborate with customers and engineering teams to develop and productize advanced protocol solutions on Palladium and Protium, define emulation/prototyping requirements for high-speed interfaces (PCIe, CXL), troubleshoot hardware/software issues, and deliver evaluations, benchmarks, and technical presentations.

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Cadence Design Systems
Cadence Design Systems
1 month ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Shape the future of system-level chip design verification in a North America hardware emulation and FPGA prototyping customer-facing role. You’ll collaborate with customers and engineering teams to develop and productize advanced protocol solutions on Palladium and Protium, define emulation/prototyping requirements for high-speed interfaces (PCIe, CXL), troubleshoot hardware/software issues, and deliver evaluations, benchmarks, and technical presentations.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with customers and frontline engineering teams to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium.
  • •Define and develop customer-specific emulation and prototyping requirements focused on leading-edge high-speed interfaces and memory protocols (e.g., PCIe, CXL).
  • •Drive development of acceleration FW and FPGA system solutions; establish robust verification methodologies and support tool operations and maintenance.
  • •Triage and resolve complex, systemic issues across the hardware/software boundary to improve driver behavior, protocol compliance, and system stability.
  • •Lead technical evaluations and create benchmarks; deliver technical presentations, white papers, and product demonstrations for existing and prospective customers.

Pay and Benefits

Salary: USD 154,000 - 286,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

  • •BS with 10+ years of experience or MS with 7+ years of experience.
  • •Strong fundamentals in digital design, computer architecture, and system-level verification.
  • •Deep technical knowledge in simulation (advanced testbench), emulation (TBA & ICE), and FPGA prototyping.
  • •Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++.
  • •Understanding of standard interconnect or IO protocols, plus strong debugging using waveforms, logs, and protocol analyzers.
Experience:7+ yearsSemiconductorHardware verificationFPGA prototyping
Education:Bachelor's
Skills:CommunicationInterpersonal skillsDebugging
Tech Stack:PalladiumProtiumFPGATBAICESystemVerilogVerilogCC++PCIeCXL

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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