Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 136,000 - 264,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Communication","Interpersonal skills"]

Own physical design for CPU cache coherent interconnect networks and last-level caches, driving synthesis and timing closure while balancing timing, area, performance, and power targets. Partner with logic design on micro-architecture feasibility, help evaluate next-generation NVIDIA coherent interconnects, and use advanced ASIC physical design flows, including floorplanning and verification activities. Contribute to platform impact across consumer graphics, self-driving, and AI computing.

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FursaFursa
NVIDIA
NVIDIA
2 days ago

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 22 hours agoStatus: Live

Job Summary

Own physical design for CPU cache coherent interconnect networks and last-level caches, driving synthesis and timing closure while balancing timing, area, performance, and power targets. Partner with logic design on micro-architecture feasibility, help evaluate next-generation NVIDIA coherent interconnects, and use advanced ASIC physical design flows, including floorplanning and verification activities. Contribute to platform impact across consumer graphics, self-driving, and AI computing.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive physical design of CPU on-chip interconnect network and last-level caches, including implementation, synthesis, and timing closure.
  • •Synthesize and achieve timing, area, performance, and power goals for the on-chip interconnect network and last-level caches.
  • •Evaluate physical design feasibility for next-generation NVIDIA coherent interconnects and system-level caches.
  • •Collaborate with logic design teams to support micro-architecture definition and feasibility.
  • •Work effectively with a dynamic global team while meeting design objectives.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually
Equity and Bonus:Equity

Key Requirements

  • •Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • •5+ years of experience in processor or related high-performance semiconductor designs.
  • •Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning, and knowledge of industry physical design tools.
  • •Experience in interconnect/cache/core design is desirable.
  • •Verilog expertise and a deep understanding of the ASIC design flow (RTL design and verification, DFT, ECO).
Experience:5+ yearsSemiconductorsHigh-performanceASIC
Education:Master's
Skills:CommunicationInterpersonal skills
Tech Stack:VerilogASIC design flowRTLSynthesisTiming analysisFloor-planningDFTECO

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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