NVIDIA

2 months ago

Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 minutes agoStatus: Live

Job Summary

Innovate and implement RTL synthesis and digital logic optimization algorithms in C++ for NVIDIA’s EDA tools, using AI/ML approaches to guide optimization. Collaborate with RTL/physical designers to improve timing, power, and area (PPA) with production-ready solutions, exploring graph-based techniques, ML methods, and high-performance software practices across design teams.

Location: Santa Clara, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Research & Scientific (R&D)

Seniority: Entry level

Key Responsibilities

•Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
•Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
•Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
•Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
•Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.

Pay and Benefits

Salary: USD 116,000 - 218,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MS or PhD in Electrical Engineering or Computer Science (or equivalent experience)
•Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization
•Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing)
•Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent)
•Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers

Experience:EDAVLSIDigital designMachine learningGPU/AI hardware

Education:Master's

Skills:C++VerilogSystemVerilogMultithreadingProfilingData structuresAlgorithmsConcurrencyTestingTemplatesSTL

Languages:English

Tech Stack:C++VerilogSystemVerilogGNNRLTemplatesSTLConcurrencyProfilingMemory management

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

2 months ago

Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 minutes agoStatus: Live

Job Summary

Location: Santa Clara, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Research & Scientific (R&D)

Seniority: Entry level

Key Responsibilities

•Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
•Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
•Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
•Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
•Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.

Pay and Benefits

Salary: USD 116,000 - 218,500 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MS or PhD in Electrical Engineering or Computer Science (or equivalent experience)
•Experience with EDA software and/or VLSI flows with focus in logic synthesis or digital optimization
•Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing)
•Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent)
•Experience in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers

Experience:EDAVLSIDigital designMachine learningGPU/AI hardware

Education:Master's

Skills:C++VerilogSystemVerilogMultithreadingProfilingData structuresAlgorithmsConcurrencyTestingTemplatesSTL

Languages:English

Tech Stack:C++VerilogSystemVerilogGNNRLTemplatesSTLConcurrencyProfilingMemory management

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor