STA Synthesis Engineer

Samsung
Bengaluru
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 4-7 yearsEducation: bachelorsSkills: ["Problem-solving","Analytical","Team-work","Communication"]

Lead timing constraint development and validation for image sensor full-chip and sub-system levels. Drive STA-based timing closure using PrimeTime/Tempus, develop scripts in TCL/Python/Perl, and collaborate with RTL/DFT/PD teams to optimize power, performance, and area while ensuring robust timing across full-chip and sub-system designs.

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FursaFursa
Samsung
Samsung
6 months ago

STA Synthesis Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Lead timing constraint development and validation for image sensor full-chip and sub-system levels. Drive STA-based timing closure using PrimeTime/Tempus, develop scripts in TCL/Python/Perl, and collaborate with RTL/DFT/PD teams to optimize power, performance, and area while ensuring robust timing across full-chip and sub-system designs.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Complete ownership of timing constraint at image sensor full chip and sub system levels, including development and release for Synthesis/PD work
  • •Timing constraint validation using various EDA tools and analysis of pre-layout and post-layout timing reports with debugging
  • •Incremental updates of constraints as required and driving timing closure with RTL, DFT and PD teams
  • •RTL PPA analysis at sub system levels for power, performance, and area trade-offs; generate and analyze reports with RTL/PD teams
  • •Develop automation scripts in TCL, Python and/or Perl to improve efficiency

Key Requirements

  • •4-7 years of experience in STA/ timing constraint development for full-chip and/or sub-system levels
  • •B.Tech/B.E/M.Tech/M.E
  • •Strong understanding of STA fundamentals, AOCV/POCV, signal integrity, cross-talk noise, process variation, timing ECO generation
  • •Hands-on experience writing timing constraints at full-chip and/or sub-system level
  • •Hands-on experience validating timing constraints and performing clean-up at full-chip and/or sub-system level
Experience:4-7 yearsSemiconductorVLSIEDA
Education:Bachelor's
Skills:Problem-solvingAnalyticalTeam-workCommunication
Tech Stack:PrimeTimeTempusTCLPythonPerlUPFSynthesisPDAOCVPOCVRTLEDA tools

Company Brief

Samsung
Global conglomerate known for consumer electronics, home appliances, semiconductors, displays, and mobile devices. Designs and manufactures a wide range of products and solutions for consumers, enterprises, and industrial customers worldwide.
Industry: Conglomerates & Holding Companies
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Seoul, South Korea
Founded: 1938
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn