ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Lead ASIC Design-for-Test (DFT) implementation in Cisco’s Silicon One development organization. Drive DFT requirements from early RTL through full implementation and post-silicon validation, partnering with front-end RTL, backend physical design, and design/verification teams. Own DFT feature implementation for ATE and in-system test, develop innovative DFT IP with cross-functional teams, and create reusable test/debug strategies across new silicon device models and die configurations.