ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Cisco
Bengaluru, Chennai, Hyderabad
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Communication","Debugging","Problem-solving","Collaboration"]

Join the Silicon One ASIC development organization as an ASIC Implementation Technical Lead focused on Design-for-Test (DFT). You’ll implement DFT features for ATE, in-system test, debug, and diagnostics; develop innovative DFT IP; and drive testability requirements from RTL through full chip integration. Work closely with design/verification and physical design teams through post-silicon validation, including ATE patterns such as P1687, and support hardware DFT signoff activities.

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Cisco
Cisco
1 month ago

ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

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Job Summary

Join the Silicon One ASIC development organization as an ASIC Implementation Technical Lead focused on Design-for-Test (DFT). You’ll implement DFT features for ATE, in-system test, debug, and diagnostics; develop innovative DFT IP; and drive testability requirements from RTL through full chip integration. Work closely with design/verification and physical design teams through post-silicon validation, including ATE patterns such as P1687, and support hardware DFT signoff activities.
Location: Bengaluru, Chennai, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Implement hardware DFT features that support ATE, in-system test, debug, and diagnostics.
  • •Develop innovative DFT IP and help coordinate testability features through full chip design integration.
  • •Collaborate with design/design-verification and physical design teams to integrate and validate test logic across implementation and post-silicon flows.
  • •Participate in creation of innovative hardware DFT and physical-design aspects for new silicon device models, including bare die and stacked die.
  • •Drive DFT and quality processes throughout implementation and post-silicon validation, with exposure to physical design signoff activities.

Key Requirements

  • •Bachelor’s or Master’s Degree in Electrical or Computer Engineering, required, with at least 12 years of experience.
  • •Knowledge of innovative trends in DFT, test, and silicon engineering.
  • •Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, and PrimeTime.
  • •Verification and debugging skills including SystemVerilog logic equivalency checking and test-timing validation; experience with gate-level simulation and simulators like VCS.
Experience:12+ years
Education:Bachelor's in Electrical or Computer Engineering
Skills:CommunicationDebuggingProblem-solvingCollaboration
Tech Stack:DFTDesign-for-TestATEJTAGScanBISTMBISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeSystemVerilogVerilogRTLLogic EquivalencyVCSTclPython

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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