Solution Validation Engineer--FPGA/SoC

AMD
San Jose
Workplace: OnsiteFull timeUSD 145,600 - 249,600 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Analytical","Problem-solving","Ownership","Mentoring"]

Build and validate FPGA-based SoC hardware/software co-design solutions across networking, storage, automotive, aerospace, and emerging AI/ML workloads. Own RTL development and pre-/post-silicon verification, integrate custom IPs with NoC and memory using Vivado/Vitis, and support board bring-up from power-on through stable bring-up. Develop embedded software for ARM Cortex or RISC-V cores, including Yocto-based embedded Linux image customization and system-level integration.

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FursaFursa
AMD
AMD
2 days ago

Solution Validation Engineer--FPGA/SoC

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Build and validate FPGA-based SoC hardware/software co-design solutions across networking, storage, automotive, aerospace, and emerging AI/ML workloads. Own RTL development and pre-/post-silicon verification, integrate custom IPs with NoC and memory using Vivado/Vitis, and support board bring-up from power-on through stable bring-up. Develop embedded software for ARM Cortex or RISC-V cores, including Yocto-based embedded Linux image customization and system-level integration.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Take a technical role across the product cycle for architecture, implementation, prototyping, validation, productization, and support, including hardware validation of IPs.
  • •Develop and verify high-performance RTL logic in SystemVerilog/Verilog focused on data/control paths.
  • •Work with Vivado/Vitis to integrate custom IPs with NoC, memory, and subsystems, and perform system-level bring-up and validation with baremetal/Linux.
  • •Build and customize embedded Linux images using Yocto-based embedded design flow, including BSP/device tree/kernel/rootfs tuning and board-specific software stack development.
  • •Support pre-/post-silicon verification and board bring-up from first power-on through stable, validated platform including debugging embedded software and FPGA fabric interactions.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •8+ years of hands-on FPGA design experience.
  • •Strong SystemVerilog/Verilog and/or VHDL with proven AMD/Xilinx FPGA work and strong Vivado proficiency.
  • •Deep knowledge of clocking, CDC, multi-clock systems, timing closure, XDC/SDC constraints, and static timing analysis.
  • •Experience with embedded Linux flows (Yocto-based Embedded Design Flow), including BSPs, device trees, and custom recipes/layers.
  • •Strong hardware debug skills (e.g., ILA, oscilloscopes, logic analyzers) and board bring-up/validation experience.
Experience:8+ yearsFPGAEmbedded LinuxHardware debugHigh-speed interfacesReal-time systems
Education:Bachelor's in computer engineering
Skills:CommunicationTeamworkAnalyticalProblem-solvingOwnershipMentoring
Tech Stack:FPGAFPGA-based systemsSoCSystemVerilogVerilogVHDLPCIeLPDDR5LPDDR6HDMI 2.1DP 2.1USB3.1UFS 4.0MIPI-CPHYImage SensorsARM CortexAPURPURISC-VEmbedded Linux

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn