Senior Mask Layout Design Engineer

NVIDIA
Taipei
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Debugging","Problem-solving","Positive energy"]

Design and verify physical masks for high-speed mixed-signal circuits in sub-micron CMOS using Cadence tools. Work with ASIC and mixed-signal engineers to tailor layouts for VLSI product integration, including floorplanning, custom layout, and signoff checks against design rules and schematics. Run and debug DRC/LVS flows with tools such as Dracula, Hercules, Calibre, and Primeyield, and customize decks as needed.

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FursaFursa
NVIDIA
NVIDIA
1 week ago

Senior Mask Layout Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Design and verify physical masks for high-speed mixed-signal circuits in sub-micron CMOS using Cadence tools. Work with ASIC and mixed-signal engineers to tailor layouts for VLSI product integration, including floorplanning, custom layout, and signoff checks against design rules and schematics. Run and debug DRC/LVS flows with tools such as Dracula, Hercules, Calibre, and Primeyield, and customize decks as needed.
Location: Taipei
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform physical layout for high-speed mixed-signal functions (e.g., PLLs, high-speed I/O, general I/O, and ESD structures) in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  • •Collaborate with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  • •Handle floorplanning and custom layout work for assigned designs.
  • •Verify layouts against design rules and schematics.
  • •Run, debug, and customize DRC/LVS checking flows using verification tools such as Dracula, Hercules, Calibre, and Primeyield.

Key Requirements

  • •BSEE or equivalent experience.
  • •Minimum of 5+ years of relevant mask design/layout experience.
  • •Deep understanding of analog circuit layout concepts in submicron CMOS technologies and expertise with Cadence custom design tools (particularly Virtuoso).
  • •Experience running and debugging DRC and LVS using tools such as Dracula, Hercules, Calibre, and Primeyield.
  • •Proficiency in scripting languages such as Perl, Python, or SKILL, and knowledge of DRC/LVS flows including customizing DRC/LVS decks.
Experience:5+ yearsMixed-signalASICVLSIDRCLVSSubmicron CMOS
Education:Bachelor's
Skills:CommunicationTeamworkDebuggingProblem-solvingPositive energy
Languages:English
Tech Stack:CadenceVirtuosoDRCLVSCadence toolsDraculaHerculesCalibrePrimeyieldPerlPythonSKILLSub-micron CMOSPLLESDASICVLSI

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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