Lead Software Engineer - Low Power Verification

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 114,800 - 213,200 annuallyFunction: Software EngineeringExperience: 4+ yearsEducation: bachelorsSkills: ["Root-cause analysis","Debugging","Communication","Technical writing","Critical evaluation"]

Develop and improve low-power verification capabilities for the Palladium and Protium emulation and prototyping platforms. Enhance UPF debug performance and usability across PPC/MC flows, scale UPF event logging and violation detection, and rebuild UPF documentation for end-to-end multi-billion-gate workflows. Collaborate with R&D, PE, and AE teams to deploy UPF solutions across key flows and help consolidate UPF debug between Palladium and Protium, including AI-assisted tooling.

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Cadence Design Systems
Cadence Design Systems
3 days ago

Lead Software Engineer - Low Power Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Develop and improve low-power verification capabilities for the Palladium and Protium emulation and prototyping platforms. Enhance UPF debug performance and usability across PPC/MC flows, scale UPF event logging and violation detection, and rebuild UPF documentation for end-to-end multi-billion-gate workflows. Collaborate with R&D, PE, and AE teams to deploy UPF solutions across key flows and help consolidate UPF debug between Palladium and Protium, including AI-assisted tooling.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Improve UPF debug features, enhancing performance and usability across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
  • •Scale UPF event logging and violation detection to capture and report more UPF events for multi-billion-gate low-power designs.
  • •Rebuild UPF documentation around end-to-end debug scenarios and workflows using valid SystemVerilog and UPF examples.
  • •Develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
  • •Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets) and consolidate/unify UPF debug across Palladium and Protium.

Pay and Benefits

Salary: USD 114,800 - 213,200 annually
Perks:Paid Leave401kEquityHealth InsuranceDentalVision

Key Requirements

  • •BS in CS, EE, or related field with 4+ years of experience (or MS with 2+ years, PhD with 1+ year, or equivalent practical experience).
  • •Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • •Strong debugging skills with root-cause analysis using logs, waveforms, traces, testcases, and user reports.
  • •Ability to read, review, and reason about C++ code and object-oriented designs.
  • •Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent) and critical evaluation of AI output.
Experience:4+ yearsEDASemiconductorsHardware verificationLow-power design
Education:Bachelor's in CS, EE, or a related field
Skills:Root-cause analysisDebuggingCommunicationTechnical writingCritical evaluation
Tech Stack:UPFIEEE 1801SystemVerilogVerilogVHDLC++CopilotClaudeCursorAI-assisted codingPPCParallel Partition CompilerMCModular Compiler

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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