Staff layout Engineer – DPG Layout

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 6+ yearsEducation: bachelorsSkills: ["Technical leadership","Mentorship","Problem-solving","Risk communication"]

Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership. Lead AI-assisted and automated layout workflows to accelerate placement, routing, and optimization. Automate and execute layout verification (DRC/LVS, Antenna, Yield, ESD, EM/IR, and quality checks), drive predictable delivery with risk mitigation, and develop AI-enabled floorplanning and consistency checks. Mentor engineers and continuously convert manual bottlenecks into scalable automation.

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FursaFursa
Micron Technology
Micron Technology
11 hours ago

Staff layout Engineer – DPG Layout

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 minutes agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership. Lead AI-assisted and automated layout workflows to accelerate placement, routing, and optimization. Automate and execute layout verification (DRC/LVS, Antenna, Yield, ESD, EM/IR, and quality checks), drive predictable delivery with risk mitigation, and develop AI-enabled floorplanning and consistency checks. Mentor engineers and continuously convert manual bottlenecks into scalable automation.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and physically implement critical analog, mixed-signal, and custom digital blocks with block-level and full-chip layout ownership.
  • •Lead AI-assisted and automated layout workflows to accelerate placement, routing, and optimization.
  • •Perform and automate layout verification activities including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR, and quality checks.
  • •Develop and deploy AI-enabled methodologies for semi-automated floorplanning, parasitic estimation, layout consistency checks, and best-practice enforcement.
  • •Drive delivery with predictable quality and risk mitigation, mentor engineers, and collaborate with Design, CAD, Verification, Reliability, and Program Management teams.

Pay and Benefits

Perks:Paid LeaveHealth InsuranceLearning BudgetWellness Stipend

Key Requirements

  • •6+ years of analog/custom layout design experience in advanced CMOS technology nodes.
  • •Hands-on expertise with Cadence Virtuoso (VLE/VXL) and Cadence Calibre DRC/LVS, including verification closure.
  • •Experience laying out critical analog blocks such as PLLs, ADCs, DACs, LDOs, bandgaps, and charge pumps.
  • •Experience with memory layouts including DRAM, SRAM, CAM, OTP, and array-to-periphery integration.
  • •Deep analog layout fundamentals (matching/symmetry, EM, latch-up, coupling/crosstalk, IR-drop, shielding, guard-ring strategies).
Experience:6+ years
Education:Bachelor's in Electronics, Electronics & Communication, or VLSI Engineering; VLSI Design, Microelectronics, or Electronics Engineering
Skills:Technical leadershipMentorshipProblem-solvingRisk communication
Tech Stack:Cadence VirtuosoVLEVXLCalibre DRCCalibre LVSSKILLPythonTCLDRCLVSAntennaESDEM/IRTOTEM

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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