ASIC DFT STA Technical Lead

Lead ASIC timing and DFT-related static timing analysis for Cisco’s Silicon One development organization. Develop and validate timing constraints across block, sub-chip, and full-chip test modes, check unconstrained endpoints, and help ensure timing quality through SDC/CDC delay checks and SDC flow development. Partner across teams to streamline STA execution with methodologies, guidelines, and checklists, and support post-silicon validation and physical design signoff exposure.