ASIC Implementation Engineer STA

Own full-chip static timing analysis sign-off for ASICs, ensuring timing closure across process, voltage, and temperature corners. Develop and maintain SDC constraints for functional and test modes, apply foundry sign-off corners, margins, and derates, and run multi-mode multi-corner analysis. Automate timing ECO generation/implementation and use Tcl, Python, and Perl to streamline analysis flows. Partner with RTL, physical design, and DFT teams to resolve timing issues and improve future methodologies.