CPU Core RTL Design Engineer

AMD
Austin
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: phdSkills: ["Problem-solving","Collaboration","Clear communication","Independent execution","Critical thinking"]

Design and optimize next-generation high-performance CPU core pipeline logic within AMD’s central core RTL team. Partner with architecture, performance, verification, and physical design teams to define microarchitecture features, balance performance/power/timing, and deliver scalable RTL methodologies. Work across the product lifecycle, supporting RTL implementation, synthesis and timing closure, and debugging pre- and post-silicon issues for client, server, and AI platforms.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
2 months ago

CPU Core RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Design and optimize next-generation high-performance CPU core pipeline logic within AMD’s central core RTL team. Partner with architecture, performance, verification, and physical design teams to define microarchitecture features, balance performance/power/timing, and deliver scalable RTL methodologies. Work across the product lifecycle, supporting RTL implementation, synthesis and timing closure, and debugging pre- and post-silicon issues for client, server, and AI platforms.
Location: Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design and implement RTL for CPU core pipeline components and related logic.
  • •Contribute to microarchitecture definition for next-generation processor cores.
  • •Collaborate with architecture, verification, and performance teams to deliver optimized designs.
  • •Analyze and improve performance, power, and timing characteristics.
  • •Support design verification, synthesis, timing closure, physical design, and debug pre- and post-silicon issues.

Key Requirements

  • •Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments.
  • •Strong understanding of modern CPU architecture, especially out-of-order cores.
  • •Expertise in logic design and high-speed processor pipeline development.
  • •Experience with load/store units or similar core subsystems.
  • •Knowledge of power-efficient/low-power design techniques and timing/power optimization, plus familiarity with synthesis and timing closure.
Experience:CPU architectureSoCASICOut-of-order
Education:PhD / Doctorate in Electrical Engineering or Computer Engineering
Skills:Problem-solvingCollaborationClear communicationIndependent executionCritical thinking
Languages:English
Tech Stack:VerilogSystemVerilogPythonTclDFT

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn