DSP Hardware Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 136,500 - 253,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: mastersSkills: ["Logic design","Self-starter","Communication","Eagerness to learn"]

Design and implement CPU/DSP/NPU hardware logic for state-of-the-art DSP products, including data-path components and pipeline architecture. Drive successful tape-outs through strong logic design skills, Verilog/SystemVerilog expertise, and end-to-end EDA flows for implementation, simulation, and verification. Leverage knowledge of DSP algorithms across audio, speech, image, video, and communications, and use scripting/perl and assembly or compiler knowledge when applicable.

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Cadence Design Systems
Cadence Design Systems
1 day ago

DSP Hardware Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Design and implement CPU/DSP/NPU hardware logic for state-of-the-art DSP products, including data-path components and pipeline architecture. Drive successful tape-outs through strong logic design skills, Verilog/SystemVerilog expertise, and end-to-end EDA flows for implementation, simulation, and verification. Leverage knowledge of DSP algorithms across audio, speech, image, video, and communications, and use scripting/perl and assembly or compiler knowledge when applicable.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and implement hardware logic for CPU/DSP/NPU or hardware accelerator designs targeting tape-out readiness.
  • •Design and optimize data-path components and pipeline architectures for DSP products.
  • •Use EDA implementation, simulation, and verification tools to validate hardware designs.
  • •Apply DSP algorithm knowledge across audio, speech, image, video, and communications domains.
  • •Use scripting (including Perl) and potentially low-level programming/compilers to support design and optimization workflows.

Pay and Benefits

Salary: USD 136,500 - 253,500 annually
Perks:Paid LeavePaid Holidays401kHealth InsuranceDentalVision

Key Requirements

  • •MS in EE or Computer Engineering with 5+ years of relevant CPU or DSP design experience.
  • •Proven logic design skills shown through successful CPU/DSP/NPU/hardware accelerator implementations or tape-outs.
  • •Strong knowledge of Verilog/SystemVerilog and EDA tools for implementation, simulation, and verification.
  • •Good knowledge of computer architecture and pipeline designs.
  • •Experience with scripting languages; good knowledge of Perl (assembly language and AI-native logic design workflows are a plus).
Experience:5+ yearsCPU designDSP designHardware acceleratorsAI-native logic design
Education:Master's in EE / Computer Engineering
Skills:Logic designSelf-starterCommunicationEagerness to learn
Tech Stack:VerilogSystemVerilogEDASimulationVerificationPerlAssemblyC/C++Computer architecturePipeline design

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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