ASIC Design Engineer – Clocks IP

NVIDIA
Santa Clara, Austin
Workplace: HybridFull timeUSD 116,000 - 218,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 2+ yearsEducation: bachelorsSkills: ["Interpersonal skills","Collaboration"]

Architect and design the clock domain for NVIDIA GPU/CPU/SoC chips, meeting functional, physical, and testing requirements. Partner with front-end, physical design/timing, and verification teams to deliver clocking RTL, evaluate clocking trade-offs across power/performance/area, and improve timing closure. Drive end-to-end ASIC execution from micro-arch through sign-off and silicon bring-up, including lab triage for clocking and programming bugs.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
NVIDIA
NVIDIA
4 days ago

ASIC Design Engineer – Clocks IP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Architect and design the clock domain for NVIDIA GPU/CPU/SoC chips, meeting functional, physical, and testing requirements. Partner with front-end, physical design/timing, and verification teams to deliver clocking RTL, evaluate clocking trade-offs across power/performance/area, and improve timing closure. Drive end-to-end ASIC execution from micro-arch through sign-off and silicon bring-up, including lab triage for clocking and programming bugs.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect the clock domain to satisfy functional, physical, and testing design requirements.
  • •Engage with multiple teams to design GPU/CPU clocks within architectural, design, and physical constraints.
  • •Improve PPA by evaluating trade-offs across DFx, physical implementation, power optimization, and timing closure, and innovating clocking topologies in RTL.
  • •Collaborate with physical design and timing teams to address high-speed clocking concerns and develop supporting solutions.
  • •Deliver clock RTL to verification/timing/DFT teams and participate in end-to-end ASIC execution through silicon bring-up, including lab triage of clocking/programming bugs.

Pay and Benefits

Salary: USD 116,000 - 218,500 annually
Equity and Bonus:Equity

Key Requirements

  • •BS in Electrical Engineering or equivalent experience (MS preferred).
  • •2+ years of relevant work experience.
  • •Deep understanding of logic optimization techniques and PPA trade-offs.
  • •Experience in RTL design (Verilog), verification, and logic synthesis.
  • •Strong coding skills in Python (or other industry-standard scripting languages).
Experience:2+ yearsASIC designSemiconductorsRTL design
Education:Bachelor's in Electrical Engineering
Skills:Interpersonal skillsCollaboration
Tech Stack:ASICGPUCPUSoCRTLVerilogLogic synthesisVerificationPythonDFxPhysical implementationPower optimizationTiming closureDFT

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
WebsiteLinkedInGlassdoor