2 days ago

SOC Clocks RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 19 hours agoStatus: Live

Job Summary

Own SOC clocking logic for next-generation networking chips, translating micro-architecture specifications into synthesizable Verilog/SystemVerilog RTL from specification through tape-out. Define clock/reset architecture, drive clock domain crossing infrastructure and CDC closure, and partner across micro-architecture, design verification, physical design, CAD, software, and DFT teams. Support clock programming sequences, DVFS, low-power/clock-shutdown flows, and ensure design quality via lint, CDC/RDC, formal checks, and synthesis QoR.

Location: Tel Aviv

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own the SOC clocking logic end-to-end, writing synthesizable Verilog/SystemVerilog RTL for clock generation/distribution, muxing/division, glitchless switching, gating, and reset synchronization through tape-out.
•Define and implement SOC clock and reset architecture with the micro-architecture team, collecting clocking requirements and turning them into a coherent, verifiable design.
•Own clock domain crossing infrastructure and drive CDC closure across the SOC.
•Partner with micro-architecture on specifications and design intent, providing feedback on implementation cost, timing, area, and power.
•Collaborate with physical design on clock tree implementation, constraints, partitioning/floorplan/timing feedback, trial synthesis, congestion/timing convergence, and physical design readiness.

Key Requirements

•B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
•3+ years of relevant experience in RTL/logic design.
•Hands-on RTL design skills in Verilog/SystemVerilog with synthesis/timing knowledge and understanding of physical implementation impacts.
•Experience taking a design from micro-architecture specification through verification and physical implementation.
•Solid understanding of clocking and reset concepts including clock gating, clock muxing/dividers, glitchless switching, reset synchronization, and clock domain crossing.

Experience:3+ yearsSemiconductorHardwareRTL designASIC

Education:Master's in Electrical Engineering or Computer Engineering

Skills:CommunicationTeamwork

Tech Stack:VerilogSystemVerilogPLLClock generationClock distributionClock muxingClock dividersGlitchless switchingClock gatingReset synchronizationClock domain crossingCDCRDCLintFormal verificationSynthesisDVFSLow-powerAutomation flowsTape-out

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

2 days ago

SOC Clocks RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 19 hours agoStatus: Live

Job Summary

Location: Tel Aviv

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own the SOC clocking logic end-to-end, writing synthesizable Verilog/SystemVerilog RTL for clock generation/distribution, muxing/division, glitchless switching, gating, and reset synchronization through tape-out.
•Define and implement SOC clock and reset architecture with the micro-architecture team, collecting clocking requirements and turning them into a coherent, verifiable design.
•Own clock domain crossing infrastructure and drive CDC closure across the SOC.
•Partner with micro-architecture on specifications and design intent, providing feedback on implementation cost, timing, area, and power.
•Collaborate with physical design on clock tree implementation, constraints, partitioning/floorplan/timing feedback, trial synthesis, congestion/timing convergence, and physical design readiness.

Key Requirements

•B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
•3+ years of relevant experience in RTL/logic design.
•Hands-on RTL design skills in Verilog/SystemVerilog with synthesis/timing knowledge and understanding of physical implementation impacts.
•Experience taking a design from micro-architecture specification through verification and physical implementation.
•Solid understanding of clocking and reset concepts including clock gating, clock muxing/dividers, glitchless switching, reset synchronization, and clock domain crossing.

Experience:3+ yearsSemiconductorHardwareRTL designASIC

Education:Master's in Electrical Engineering or Computer Engineering

Skills:CommunicationTeamwork

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor