Sr Principal Application Engineer - Design Verification

Cadence Design Systems
Yokohama
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-6 yearsSkills: ["Verilog","VHDL","SystemVerilog","HDL simulators","UVM","Jasper","AI for design and verification","Emulator","Accelerator","English","Japanese"]

Senior-level design verification engineer responsible for Verilog/VHDL IP/SoC verification, SystemVerilog/UVM, and AI-assisted design verification. Collaborates with sales and engineering to scope Cadence SoC verification solutions, conducts evaluations and benchmarks, trains customers, and provides deep technical expertise to address complex inquiries while aligning product direction with customer needs.

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Cadence Design Systems
Cadence Design Systems
3 months ago

Sr Principal Application Engineer - Design Verification

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Last checked: 1 hour agoStatus: Live

Job Summary

Senior-level design verification engineer responsible for Verilog/VHDL IP/SoC verification, SystemVerilog/UVM, and AI-assisted design verification. Collaborates with sales and engineering to scope Cadence SoC verification solutions, conducts evaluations and benchmarks, trains customers, and provides deep technical expertise to address complex inquiries while aligning product direction with customer needs.
Location: Yokohama
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Work with Sales to identify and scope opportunities for Cadence SoC Verification, AI, simulation Emulation, and Acceleration products.
  • •Plan, execute and manage technical evaluations and benchmark with customers.
  • •Train, ramp-up and accompany customer projects and conduct trainings, presentations, and demos as needed.
  • •Provide technical expertise to address client queries requiring expert involvement.
  • •Collaborate with corporate engineering and sales/marketing to align on customer requirements for product direction/improvement.

Key Requirements

  • •4-6+ years of experience in Verilog/VHDL design for IP or SoC at chip level.
  • •Strong verification knowledge with SystemVerilog/VHDL and HDL simulators.
  • •Experience with formal verification; Jasper experience is a plus.
Experience:4-6 yearsSemiconductorsEDASoCVerificationHardware
Skills:VerilogVHDLSystemVerilogHDL simulatorsUVMJasperAI for design and verificationEmulatorAcceleratorEnglishJapanese
Languages:JapaneseEnglish
Tech Stack:VerilogVHDLSystemVerilogHDL simulatorsUVMJasperAIEmulatorAccelerator

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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