Senior DFT Engineer

Cadence Design Systems
Bengaluru, Noida
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 5-15 yearsSkills: ["Problem-solving","Teamwork","Communication"]

Seeking a SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) to drive scan chain insertion, MBIST, and ATPG across Cadence flows. You will work on DFT insertion flows, LBIST and related technologies, verify ATPG testbenches, and collaborate with Architecture, Design, and external teams to ensure robust test coverage in a fast-paced, cross-location environment.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
2 years ago

Senior DFT Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Seeking a SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) to drive scan chain insertion, MBIST, and ATPG across Cadence flows. You will work on DFT insertion flows, LBIST and related technologies, verify ATPG testbenches, and collaborate with Architecture, Design, and external teams to ensure robust test coverage in a fast-paced, cross-location environment.
Location: Bengaluru, Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

  • •Incorporate and optimize DFT techniques (scan chain insertion, compression scan, MBIST) into SoC/ASIC designs.
  • •Develop and validate ATPG patterns to meet design test-coverage goals and debug failures.
  • •Verify ATPG testbenches and analyze simulation mis-compares to identify root causes.
  • •Collaborate with Architecture, Design, and cross-functional teams to ensure robust DFT implementations and tool flow familiarity (Cadence).
  • •Independently execute DFT tasks, track quality metrics, and contribute to continuous improvement of test methodologies.

Key Requirements

  • •Must be able to obtain and maintain a Department of Defense classified clearance.
  • •5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT).
  • •Intimate knowledge of DFT insertion flows.
  • •Basic scan chain insertion using synthesis or other software tools.
  • •Experience in compression scan insertion, LBIST and other scan technologies.
Experience:5-15 yearsSemiconductorDFTSoCASIC
Skills:Problem-solvingTeamworkCommunication
Tech Stack:VerilogDFTATPGLBISTJTAG 1149.1/6IEEE1500IEEE1687CadenceSynthesisVerification

Eligibility

Security Clearance:DoD clearance

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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