Sr. RTL Design Engineer (Silicon Engineering)

SpaceX
United States
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","HDL simulators","HDL Lint tools","ASIC","SoC","Clock domain crossings","Power optimization","Python"]

Senior RTL Design Engineer for SpaceX's silicon team building next-generation ASICs for Starlink. You will define micro-architecture, write RTL in Verilog/SystemVerilog, and collaborate with verification, timing, and physical teams to deliver verified, synthesis-clean designs for space and ground infrastructure. This role focuses on RTL implementation, IP timing, and silicon bring-up in a cross-disciplinary environment.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
SpaceX
SpaceX
4 months ago

Sr. RTL Design Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Senior RTL Design Engineer for SpaceX's silicon team building next-generation ASICs for Starlink. You will define micro-architecture, write RTL in Verilog/SystemVerilog, and collaborate with verification, timing, and physical teams to deliver verified, synthesis-clean designs for space and ground infrastructure. This role focuses on RTL implementation, IP timing, and silicon bring-up in a cross-disciplinary environment.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • •Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • •Work closely with verification team to ensure all aspects of the design are covered and verified
  • •Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • •Participate in silicon bring-up and validation

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • •5+ years of experience in RTL implementation
  • •Ability to solve complex problems including clock domain crossings and power optimization
  • •ASIC/SoC system integration experience
  • •Experience with embedded CPU subsystems
Experience:5+ yearsSpaceStarlinkASICSilicon
Education:Bachelor's
Skills:VerilogSystemVerilogHDL simulatorsHDL Lint toolsASICSoCClock domain crossingsPower optimizationPython
Languages:English
Tech Stack:VerilogSystemVerilogHDL simulatorsHDL Lint toolsASICSoCPython

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
Glassdoor
Glassdoor: 4.2
WebsiteLinkedIn