Sr. Silicon Design Engineer

AMD
Austin
Workplace: OnsiteFull timeUSD 106,470 - 182,520 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: mastersSkills: ["Technical leadership","Problem-solving"]

Develop and maintain block-level RTL IP and MP subsystem feature specs, micro-architecture, and synthesizable RTL design methodology. Build, debug, and verify RTL using C-DPI directed test methodology and verification team testbenches to achieve feature and coverage closure. Triage and resolve retrogressions and integration issues across SoC Integration, SoC DV, and post-silicon validation, providing advanced-level technical leadership in IP functionality and design methodology.

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FursaFursa
AMD
AMD
3 days ago

Sr. Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Develop and maintain block-level RTL IP and MP subsystem feature specs, micro-architecture, and synthesizable RTL design methodology. Build, debug, and verify RTL using C-DPI directed test methodology and verification team testbenches to achieve feature and coverage closure. Triage and resolve retrogressions and integration issues across SoC Integration, SoC DV, and post-silicon validation, providing advanced-level technical leadership in IP functionality and design methodology.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop and maintain block-level RTL IP and MP subsystem feature specs, micro-architecture, and synthesizable RTL design methodology/infrastructure.
  • •Develop, debug, and verify RTL designs using C-DPI directed tests and/or verification testbenches to achieve feature closure against coverage metrics.
  • •Triage retrogressions, debug simulations, analyze coverage, and resolve technical issues with design/verification and other teams to reach design and design-rule closure (linting, timing, DFT, DFP, and related rules).
  • •Participate in verification testbench and test plan specification; influence testbench architecture and review/improve feature and coverage test plans.
  • •Debug and resolve integration issues across SoC Integration, SoC DV, and post-silicon validation, providing advanced technical leadership in IP functionality and design methodology development.

Pay and Benefits

Salary: USD 106,470 - 182,520 annually

Key Requirements

  • •Master’s degree (or foreign equivalent) in Computer Engineering, Electrical Engineering, Electronic Engineering, or a related field.
  • •One (1) year of experience in the job offered or a closely related engineering role.
  • •Hardware verification and logic/circuit design experience.
  • •RTL design or coding, including Verilog or VHDL, and RTL design methodology.
  • •Experience with CAD and ASIC design tools (synthesis, simulation, equivalence checking, static timing analysis) plus front-end EDA tools; C++ and Python; object-oriented design; data structures.
Experience:1+ yearsSemiconductorsHardware verification
Education:Master's
Skills:Technical leadershipProblem-solving
Languages:English
Tech Stack:RTLBlock-level RTLMicro-architectureC-DPIVerilogVHDLASIC design toolsSynthesisSimulationEquivalence checkingStatic timing analysisCAD toolsFront-end EDA toolsC++PythonObject-oriented designData structuresLintingTimingDFT

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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