Senior Functional Verification Engineer (Graphics/Multimedia)

AMD
Hyderabad
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Creative Production (Video/Audio/Photo)Experience: 12+ yearsEducation: bachelorsSkills: ["Communication","Problem-solving","Detail-oriented","Debugging","Mentoring"]

Join AMD’s Client/Graphics Group to drive pre-silicon verification for full-chip, blocks, multi-chip, and system-level designs. Specify verification plans at SoC/IP level, develop complex self-checking, reusable, automated verification environments, and build constrained-random generators with reference models. Work hands-on on functional verification scope, mentor junior team members, and debug functional simulations using strong Verilog/SystemVerilog skills, coverage analysis, and test plan development.

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FursaFursa
AMD
AMD
1 day ago

Senior Functional Verification Engineer (Graphics/Multimedia)

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Last checked: 4 hours agoStatus: Live

Job Summary

Join AMD’s Client/Graphics Group to drive pre-silicon verification for full-chip, blocks, multi-chip, and system-level designs. Specify verification plans at SoC/IP level, develop complex self-checking, reusable, automated verification environments, and build constrained-random generators with reference models. Work hands-on on functional verification scope, mentor junior team members, and debug functional simulations using strong Verilog/SystemVerilog skills, coverage analysis, and test plan development.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Creative Production (Video/Audio/Photo)
Seniority: Mid level

Key Responsibilities

  • •Participate in pre-silicon verification for full chip, blocks, multi-chip, and system-level verification.
  • •Specify design verification plans at SoC level and IP level, and specify or review verification plans for complex ASIC blocks.
  • •Develop complex verification environments using coverage/assertions-based verification methodology (self-checking, reusable, automated) for full-chip and block levels.
  • •Create and execute functional verification scope using constrained random generators and reference models.
  • •Mentor junior team members and collaborate with internal/external stakeholders to drive solutions.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •Minimum 12+ years of experience in ASIC Design Verification.
  • •Excellent knowledge of ASIC Design Flow and SoC architecture.
  • •Experience developing complex testbenches/models in Verilog, SystemVerilog, or SystemC.
  • •Experience with coverage-based verification methodology, including writing test plans and test cases.
  • •Strong debug skills in functional simulations and experience with random test generation, coverage analysis, and failure debug.
Experience:12+ yearsASIC design verificationSemiconductors
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationProblem-solvingDetail-orientedDebuggingMentoring
Languages:English
Tech Stack:VerilogSystemVerilogSystemCPLIC/C++PerlShell scriptsASICSoCUPFNLP

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn