Cadence Design Systems

2 months ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Lead functional verification for the DDR Subsystem (Memory Controller and PHY IP) at Cadence, focusing on DDR/HBM/LPDDR verification using SV/UVM. Deliver demos/testbenches, ensure code and functional coverage, mentor the team in Bangalore, and drive quality to meet schedules in a fast-paced hardware verification environment.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Functional verification of the DDR Subsystem comprising DDR Memory Controller and PHY IP, ensuring defects are identified and resolved.
•Extend the verification environment with new features, manage customer configurations, and drive regression coverage.
•Provide Demosim testbench with standard test patterns to aid customer integration of IPs.
•Review technical deliverables, guide team members to meet quality and schedule, and mentor project staff.
•Track verification progress, identify risks, implement mitigation plans, and contribute to process improvements.

Key Requirements

•BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer.
•8+ years of Design Verification experience with SV/UVM.
•Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development.
•Strong hands-on UVM and SystemVerilog coding experience and verification environment development; RTL Design experience using Verilog.
•Prior IP verification experience of memory IP (DDR/HBM/LPDDR) would be an added advantage.

Experience:8+ yearsSemiconductorsHardware verificationVLSI

Education:Bachelor's in Electrical / Electronics / VLSI

Skills:CommunicationPresentationTeamworkInterpersonalVerbal

Languages:English

Tech Stack:SVUVMSystemVerilogVerilogDemosimDDRHBMLPDDR

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

2 months ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Functional verification of the DDR Subsystem comprising DDR Memory Controller and PHY IP, ensuring defects are identified and resolved.
•Extend the verification environment with new features, manage customer configurations, and drive regression coverage.
•Provide Demosim testbench with standard test patterns to aid customer integration of IPs.
•Review technical deliverables, guide team members to meet quality and schedule, and mentor project staff.
•Track verification progress, identify risks, implement mitigation plans, and contribute to process improvements.

Key Requirements

•BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer.
•8+ years of Design Verification experience with SV/UVM.
•Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development.
•Strong hands-on UVM and SystemVerilog coding experience and verification environment development; RTL Design experience using Verilog.
•Prior IP verification experience of memory IP (DDR/HBM/LPDDR) would be an added advantage.

Experience:8+ yearsSemiconductorsHardware verificationVLSI

Education:Bachelor's in Electrical / Electronics / VLSI

Skills:CommunicationPresentationTeamworkInterpersonalVerbal

Languages:English

Tech Stack:SVUVMSystemVerilogVerilogDemosimDDRHBMLPDDR

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor