Lead Software Engineer - Low-Power Verification

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 114,800 - 213,200 annuallyFunction: Software EngineeringExperience: 4+ yearsEducation: bachelorsSkills: ["Technical writing","Critical evaluation"]

Build and improve low-power verification capabilities for the Palladium and Protium emulation/prototyping platforms. Own parts of the UPF compilation flow—boost performance, reduce instrumented capacity, and add correctness self-checks across PPC and Modular Compiler flows, including Dielet UPF support. Rebuild and validate end-to-end UPF documentation and examples, and partner with R&D teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets).

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Cadence Design Systems
Cadence Design Systems
4 days ago

Lead Software Engineer - Low-Power Verification

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live
Reposted: similar role first listed 5 days ago

Job Summary

Build and improve low-power verification capabilities for the Palladium and Protium emulation/prototyping platforms. Own parts of the UPF compilation flow—boost performance, reduce instrumented capacity, and add correctness self-checks across PPC and Modular Compiler flows, including Dielet UPF support. Rebuild and validate end-to-end UPF documentation and examples, and partner with R&D teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets).
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Contribute to the UPF compilation flow by improving performance, reducing instrumented capacity, and adding self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
  • •Rebuild UPF documentation around end-to-end compilation workflows using valid SystemVerilog and UPF examples, and keep code and docs in sync via example-driven checks.
  • •Collaborate with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets) with UPF in 2- and 4-state.
  • •Consolidate and unify UPF compilation across Palladium and Protium.

Pay and Benefits

Salary: USD 114,800 - 213,200 annually
Perks:Paid Leave401kEquityHealth InsuranceDentalVision

Key Requirements

  • •BS in Computer Science, EE, or related field with 4+ years of experience (or MS with 2+ years; PhD with 1+ year; or equivalent practical experience).
  • •Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • •Ability to read, review, and reason about C++ code and object-oriented designs.
  • •Scripting experience in Perl, Tcl/Tk, and/or Python.
  • •Strong technical writing skills to author user guides, specifications, and workflow-first documentation.
Experience:4+ years
Education:Bachelor's
Skills:Technical writingCritical evaluation
Tech Stack:UPFIEEE 1801SystemVerilogVerilogVHDLC++PerlTcl/TkPythonCopilotClaudeCursor

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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