Senior Formal Verification Engineer
Santa Clara, Austin
Workplace: HybridFull timeUSD 168,000 - 310,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 7+ yearsEducation: mastersSkills: ["Verilog","SystemVerilog","TCL","Perl","Python","Verilog/SystemVerilog","Temporal logic","Assertions"]Senior Formal Verification Engineer to verify design and implementation of high-performance chip interconnects. You will develop formal verification methodologies, write testplans, build abstraction models, and drive verification tools. Collaborate with architects, designers, and pre-/post-silicon teams to ensure functional correctness and full/coarse proofs, leveraging Verilog/SystemVerilog, TCL, Python, and formal tools in a hybrid, US-based environment.
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