Senior Full Chip Layout and Physical Verification CAD Engineer
NVIDIA
Tel Aviv
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Python","Tcl","Shell","Make","Linux","EDA tools","ICC2","FC","Innovus","ICV","Calibre","DRC","LVS","ANT","ERC","DFM"]Senior hardware design engineer responsible for full-chip physical design methodologies, physical verification, and tapeout activities for networking chips and SoCs, collaborating across layout owners and project managers to ensure high-quality convergence and innovative solutions.
