RTL Design Engineer (Silicon Engineering)

SpaceX
Irvine
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Team-player","Can-do attitude","Cross-functional collaboration","Communication"]

Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participating in integration tasks using Verilog/SystemVerilog. Lead full ASIC/FPGA design lifecycle from concept through microarchitecture and lab validation, while collaborating with cross-functional teams to advance Starlink hardware for space and ground infrastructure.

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FursaFursa
SpaceX
SpaceX
4 months ago

RTL Design Engineer (Silicon Engineering)

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Last checked: 5 hours agoStatus: Live

Job Summary

Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participating in integration tasks using Verilog/SystemVerilog. Lead full ASIC/FPGA design lifecycle from concept through microarchitecture and lab validation, while collaborating with cross-functional teams to advance Starlink hardware for space and ground infrastructure.
Location: Irvine
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
  • •Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
  • •Engage in high-level architectural design for FPGA and ASICs
  • •Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more

Pay and Benefits

Perks:Health InsuranceVisionDental

Key Requirements

  • •Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • •1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
  • •Master’s in Electrical/Computer Engineering or related field (preferred)
  • •ASIC/FPGA system integration experience
  • •Proficiency in Python for scripting
Experience:1+ yearsSpaceAerospaceTelecommunications
Education:Bachelor's
Skills:Team-playerCan-do attitudeCross-functional collaborationCommunication
Languages:English
Tech Stack:SystemVerilogVerilogVHDLPythonHDL simulatorsAXIAHBAPBEDA toolsFPGAASIC

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
Glassdoor
Glassdoor: 4.2
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