SR ASIC Design Engineer - NoC & AXI Interconnect
AMD
Santa Clara
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["SystemVerilog","Verilog","Perl","Python","Shell scripting","RTL design","VCS","NoC","AXI","ACE","APB","Queuing system design","Buffer management"]Contribute to ASIC design for high-performance network chips (AINIC and DPU) as part of the NTSG ASIC Design Team. In the front-end design/integration role, collaborate with architecture, IP design, and Physical Design teams to achieve first-pass silicon success. You’ll work closely with senior engineers, delivering precise, detail-oriented work on NoC, AXI/ACE/APB interfaces, and queuing systems.
