Staff layout Engineer – DPG Layout

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: OtherExperience: 6+ yearsEducation: mastersSkills: ["Technical leadership","Mentoring","Communication","Problem-solving","Collaboration"]

Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, taking responsibility for block-level and full-chip layout. Lead layout implementation with AI-assisted and automated workflows to accelerate placement, routing, and optimization. Automate and execute physical verification (DRC/LVS and more), drive on-time delivery with predictable quality and risk planning, and scale AI-enabled methodologies for layout tasks and quality enforcement. Mentor engineers and collaborate across Design, CAD, Verification, Reliability, and Program Management.

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FursaFursa
Micron Technology
Micron Technology
3 weeks ago

Staff layout Engineer – DPG Layout

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 hours agoStatus: Live

Job Summary

Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, taking responsibility for block-level and full-chip layout. Lead layout implementation with AI-assisted and automated workflows to accelerate placement, routing, and optimization. Automate and execute physical verification (DRC/LVS and more), drive on-time delivery with predictable quality and risk planning, and scale AI-enabled methodologies for layout tasks and quality enforcement. Mentor engineers and collaborate across Design, CAD, Verification, Reliability, and Program Management.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Seniority: Mid level

Key Responsibilities

  • •Own physical implementation of analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership.
  • •Lead AI-assisted and automated layout implementation workflows to improve placement, routing, and optimization.
  • •Perform and automate layout verification activities (e.g., DRC, LVS, antenna, yield, ESD, EM/IR, and quality checks) to achieve verification closure.
  • •Drive on-time delivery of blocks and partition-level layouts with predictable quality and risk mitigation plans.
  • •Develop and scale AI-enabled methodologies and automation for floorplanning, parasitic estimation, layout consistency checks, best-practice enforcement, and repetitive task elimination.

Key Requirements

  • •6+ years of analog/custom layout design experience in advanced CMOS technology nodes.
  • •Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands-on verification closure.
  • •Proven layout experience for critical analog blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, and charge pumps.
  • •Hands-on memory layout experience (DRAM, SRAM, CAM, OTP) with understanding of array-to-periphery integration.
  • •Deep understanding of analog layout fundamentals (matching/symmetry, EM, latch-up, coupling/crosstalk, IR-drop, shielding, guard rings) and AI-driven automation scaling for complex workflows.
Experience:6+ yearsAnalog layoutMixed-signalCustom layoutAdvanced CMOSMemory layoutAI-driven automationPhysical verification
Education:Master's in VLSI Design, Microelectronics, Electronics, Electronics & Communication
Skills:Technical leadershipMentoringCommunicationProblem-solvingCollaboration
Tech Stack:Cadence VirtuosoVLEVXLCalibreDRCLVSAntennaESDTOTEMEM/IRSKILLPythonTCLAgentic AIAI-assisted workflowsCopilot-based assistants

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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