PMTS Silicon Design Engineer

Experienced Full Chip SoC Timing Lead responsible for end-to-end timing closure of complex ASIC/SoC designs. Lead synthesis-to-tapeout timing signoff, develop and validate timing constraints, perform STA, drive MMMC timing methodology, and collaborate with RTL, PD, CTS/DFT, power and signoff teams to ensure robust, clock-efficient designs across multiple technology nodes.