ASIC Implementation Engineer STA

Own full-chip static timing analysis and timing closure for ASICs, ensuring performance targets are met across all PVT corners. Develop and maintain SDC constraints for functional and test modes, incorporate foundry sign-off corners, and analyze advanced timing effects like AOCV/POCV, crosstalk, and IR-drop. Run and manage multi-mode multi-corner (MMMC) scenarios, automate timing ECO generation, and collaborate with RTL, physical design, and DFT teams.