ASIC Implementation Engineer STA

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Problem-solving","Communication","Teamwork"]

Own full-chip static timing analysis and timing closure for ASICs, ensuring performance targets are met across all PVT corners. Develop and maintain SDC constraints for functional and test modes, incorporate foundry sign-off corners, and analyze advanced timing effects like AOCV/POCV, crosstalk, and IR-drop. Run and manage multi-mode multi-corner (MMMC) scenarios, automate timing ECO generation, and collaborate with RTL, physical design, and DFT teams.

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FursaFursa
Broadcom
Broadcom
1 month ago

ASIC Implementation Engineer STA

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Last checked: 17 days agoStatus: Live

Job Summary

Own full-chip static timing analysis and timing closure for ASICs, ensuring performance targets are met across all PVT corners. Develop and maintain SDC constraints for functional and test modes, incorporate foundry sign-off corners, and analyze advanced timing effects like AOCV/POCV, crosstalk, and IR-drop. Run and manage multi-mode multi-corner (MMMC) scenarios, automate timing ECO generation, and collaborate with RTL, physical design, and DFT teams.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Own full-chip timing sign-off by performing quality checks across PVT corners to achieve timing closure.
  • •Author, validate, and maintain SDC constraints for functional and test modes including Scan, MBIST, and ATPG.
  • •Incorporate foundry guidelines into timing analysis flows by adding sign-off corners, margins, and derates.
  • •Perform advanced timing analysis using concepts like AOCV/POCV and IR-drop aware STA, including signal integrity (crosstalk).
  • •Automate and implement timing ECOs and collaborate with RTL, physical design, and DFT teams to resolve timing issues and define guard-banding requirements.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEquity

Key Requirements

  • •Bachelor’s degree in Electrical Engineering or Computer engineering.
  • •Minimum 12 years of hands-on ASIC STA experience and timing constraints development, including timing closure with Cadence or Synopsys tools.
  • •Experience driving timing closure by managing on-chip variation derates and optimizing multi-mode multi-corner constraints.
  • •Proficiency in scripting languages such as Tcl and Python (Perl/Shell also acceptable).
  • •Strong problem-solving skills and precise technical communication, with attention to every technical aspect.
Experience:12+ years
Education:Bachelor's
Skills:Problem-solvingCommunicationTeamwork
Tech Stack:ASICStatic Timing Analysis (STA)TclPythonPerlShellSDCCadenceSynopsysAOCVPOCVSignal IntegrityCrosstalkIR-dropMMMCTiming ECOECOATPGScanMBIST

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn