IC Design Engineer

Lead Broadcom’s right-first-time physical design methodology for SoC in 5nm and lower technologies. Drive block/level layout and physical design tasks including floorplanning, partitioning, placement, clock tree synthesis, routing, extraction, and physical verification toward STA closure. Implement timing and functional ECOs, improve quality and TAT through automation, and adapt or build automation flows. Work with backend digital design flows and EDA toolchains across P&R, PV, STA, and ECO stages.