Lead RTL Design & Validation Engineer with DDR protocols exp

AMD
Hyderabad
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 9+ yearsEducation: mastersSkills: ["Cross-functional collaboration","Communication","Teamwork","Problem-solving"]

Plan, build, and execute RTL design and validation for new and existing features across AMD’s DDR IPs and custom IPs. Collaborate with cross-functional teams to integrate DDR memory controller calibration solutions—RTL logic, firmware routines, and calibration algorithms—into system-level validation and bring-up environments. Deliver reliable calibration performance, improve accuracy and convergence under PVT variations, and lead system bring-up/debug to resolve memory training and stability issues.

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FursaFursa
AMD
AMD
2 days ago

Lead RTL Design & Validation Engineer with DDR protocols exp

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Plan, build, and execute RTL design and validation for new and existing features across AMD’s DDR IPs and custom IPs. Collaborate with cross-functional teams to integrate DDR memory controller calibration solutions—RTL logic, firmware routines, and calibration algorithms—into system-level validation and bring-up environments. Deliver reliable calibration performance, improve accuracy and convergence under PVT variations, and lead system bring-up/debug to resolve memory training and stability issues.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Plan and execute RTL design and validation for DDR IPs and custom IP features.
  • •Design and implement firmware solutions for DDR memory controller calibration across DDR standards.
  • •Develop and refine calibration algorithms to improve accuracy, convergence speed, and adaptability under PVT variations.
  • •Create and run validation plans for calibration firmware, algorithms, and custom IPs; perform system-level bring-up and debug for training and stability issues.
  • •Partner with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience.
  • •Digital RTL design experience in Verilog/SystemVerilog and understanding of system-level architecture (e.g., AXI/AHB).
  • •Experience with DDR memory technologies (DDR4, DDR5, LPDDR) and JEDEC standards, including memory controller and PHY exposure across IP vendors.
  • •Hands-on experience implementing DRAM/memory controller initialization code and training/calibration software for DDR PHYs and memory subsystems.
  • •Experience with version control (Perforce, ICManage, or Git) and system bring-up/debug validation activities (e.g., lab tools like high-speed scopes).
Experience:9+ yearsDDRSemiconductorMemory systemsHardware validation
Education:Master's in EE/CE
Skills:Cross-functional collaborationCommunicationTeamworkProblem-solving
Languages:English
Tech Stack:VerilogSystemVerilogRTL designAXIAHBCPerforceICManageGitHigh-speed scopeLogic analyzersSTA (timing analysis)

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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