2 days ago

ASIC Engineering Technical Leader

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Drive the test vehicle strategy and design for advanced semiconductor packaging technologies, focusing on 2.5D/3D integration and heterogeneous integration. Partner with assembly, substrate, and OSAT suppliers to define integration flow, qualify new package technologies, and optimize materials/design rules for warpage, stress, and SI/PI performance. Resolve design challenges with internal physical design teams using DfM/DfR principles and advance reliable large-body, large-die assembly solutions.

Location: Taipei

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Develop test vehicle strategy and design for advanced package technologies using 2.5D/3D integration stacking processes.
•Engage with assembly suppliers to understand assembly process, module design rules, and requirements.
•Define assembly process integration and flow for advanced heterogeneous integration solutions including Co-packaged Optics and Co-packaged Copper.
•Develop plans to evaluate and qualify new package technologies.
•Collaborate with substrate suppliers and internal teams to optimize materials/design rules for warpage, stress, SI/PI performance, and implement DfM/DfR solutions, including reliability and board-mount process considerations.

Key Requirements

•BS/MS/PhD in Mechanical Engineering, Materials Science, Physics, or a closely related field.
•10+ years of progressive experience in Semiconductor Packaging and Assembly, leading technical projects or initiatives.
•Proven experience developing and executing advanced packaging technologies, including 2.5D/3D process integration, heterogeneous integration, wafer-level packaging, and qualification methods.
•Comprehensive knowledge of advanced CoWoS package assembly and manufacturing flow.
•Experience with substrate manufacturing processes, design rules, and materials for high layer count substrate stack-ups, including impacts to device-level power and signal integrity.

Experience:10+ yearsSemiconductor packagingAssemblyHeterogeneous integration

Education:PhD / Doctorate in Mechanical Engineering, Materials Science, Physics

Skills:Problem-solvingData analysisCommunicationPresentationInfluencing

Tech Stack:2.5D3D3D integrationHeterogeneous integrationWafer-level packagingPackage technology qualificationCoWoSCo-packaged OpticsCo-packaged CopperSubstrate manufacturingDfMDfRSI/PI performanceFMEA8DStatistical process controlOSATReliabilityBoard-mount process

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

2 days ago

ASIC Engineering Technical Leader

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: Taipei

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Develop test vehicle strategy and design for advanced package technologies using 2.5D/3D integration stacking processes.
•Engage with assembly suppliers to understand assembly process, module design rules, and requirements.
•Define assembly process integration and flow for advanced heterogeneous integration solutions including Co-packaged Optics and Co-packaged Copper.
•Develop plans to evaluate and qualify new package technologies.
•Collaborate with substrate suppliers and internal teams to optimize materials/design rules for warpage, stress, SI/PI performance, and implement DfM/DfR solutions, including reliability and board-mount process considerations.

Key Requirements

•BS/MS/PhD in Mechanical Engineering, Materials Science, Physics, or a closely related field.
•10+ years of progressive experience in Semiconductor Packaging and Assembly, leading technical projects or initiatives.
•Proven experience developing and executing advanced packaging technologies, including 2.5D/3D process integration, heterogeneous integration, wafer-level packaging, and qualification methods.
•Comprehensive knowledge of advanced CoWoS package assembly and manufacturing flow.
•Experience with substrate manufacturing processes, design rules, and materials for high layer count substrate stack-ups, including impacts to device-level power and signal integrity.

Experience:10+ yearsSemiconductor packagingAssemblyHeterogeneous integration

Education:PhD / Doctorate in Mechanical Engineering, Materials Science, Physics

Skills:Problem-solvingData analysisCommunicationPresentationInfluencing

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor