Lead Hardware Engineer - DFT IP R&D

Cadence Design Systems
Noida, Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 4-6 yearsEducation: mastersSkills: ["Verilog","SystemVerilog","UVM","Verilog/SV simulators","Linters","CDC checkers","SystemVerilog assertions","Python","Perl","DFT methodologies","Synthesis","STA"]

Lead hardware engineer for the MODUS DFT product line, focusing on RTL/DFT design and verification, EDA tool integration, and performance optimization. Responsibilities span RTL development, test bench creation, debugging, and collaboration with R&D to advance DFT IP capabilities, with mentoring to develop problem-solving skills in a cutting-edge EDA environment.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Lead Hardware Engineer - DFT IP R&D

âś“ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Lead hardware engineer for the MODUS DFT product line, focusing on RTL/DFT design and verification, EDA tool integration, and performance optimization. Responsibilities span RTL development, test bench creation, debugging, and collaboration with R&D to advance DFT IP capabilities, with mentoring to develop problem-solving skills in a cutting-edge EDA environment.
Location: Noida, Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Designing and verifying Verilog/SystemVerilog/UVM RTL and test benches for DFT IP features, including new DFT IPs, full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels.
  • •Providing R&D support to application and product engineers, including problem analysis, debugging, and the development of new features to optimize synthesis results for timing, area, and power.
  • •There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!
  • •Mentoring and support to enable contribution to the large EDA problem domain and to develop problem-solving skills into professional engineering skills.
  • •Development responsibilities include designing, developing, troubleshooting, debugging and supporting the MODUS software product.

Key Requirements

  • •Proficient in RTL design using Verilog and SystemVerilog, with experience in design-for-testability (DFT) features such as full scan, compressed/uncompressed scan, memory BIST, JTAG, IEEE 1500, boundary scan; strong debugging and verification skills.
Experience:4-6 yearsEDADFTRTLSemiconductors
Education:Master's in EE/ECE/CS
Skills:VerilogSystemVerilogUVMVerilog/SV simulatorsLintersCDC checkersSystemVerilog assertionsPythonPerlDFT methodologiesSynthesisSTA
Tech Stack:VerilogSystemVerilogUVMVerilog/SV simulatorsLintersCDC checkersSystemVerilog assertionsPythonPerlDFTSynthesisSTAJTAGIEEE 1500Memory BIST

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor