New Graduate Engineer, Silicon Engineering

SpaceX
Palo Alto, Irvine, Redmond
Workplace: OnsiteFull timeUSD 125,000 - 195,000 annuallyFunction: Hardware, Embedded & Systems EngineeringSkills: ["Hands-on","Self-starter","Execution","Collaboration"]

Design and verify next-generation silicon for Starlink, working across ASIC/FPGA flows, RF/Analog IC, digital signal processing, and physical design. You’ll execute hands-on verification tasks, contribute to RTL and bring-up in the lab, help partition RFIC hardware/software functions, and support synthesis, signoff checks, and future silicon tapeouts. Opportunities are available in Palo Alto, Irvine, and Redmond.

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FursaFursa
SpaceX
SpaceX
21 hours ago

New Graduate Engineer, Silicon Engineering

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Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Design and verify next-generation silicon for Starlink, working across ASIC/FPGA flows, RF/Analog IC, digital signal processing, and physical design. You’ll execute hands-on verification tasks, contribute to RTL and bring-up in the lab, help partition RFIC hardware/software functions, and support synthesis, signoff checks, and future silicon tapeouts. Opportunities are available in Palo Alto, Irvine, and Redmond.
Location: Palo Alto, Irvine, Redmond
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Graduate level

Key Responsibilities

  • •Participate in ASIC/FPGA design and verification flows, contributing to design architecture, RTL implementation and/or verification, and emulation.
  • •Bring up and validate ASICs and FPGAs in the lab, including writing embedded software using C/C++ and/or Python.
  • •Simulate and model RFIC systems, derive subsystem and circuit specifications, and develop RF/microwave circuits in SiGe or CMOS processes.
  • •Develop RTL designs for DSP and digital communication system blocks, and verify against fixed-point MATLAB models.
  • •Perform physical design tasks (synthesis, floor planning, place and route, signoff checks) and support silicon tapeouts for future Starlink SOCs.

Pay and Benefits

Salary: USD 125,000 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVisionDental401kLife InsuranceDisability InsurancePaid ParentalPaid Leave

Key Requirements

  • •Graduating with a bachelor’s degree, master’s degree, or PhD in 2026 or 2027.
  • •Bachelor’s degree in an engineering discipline, mathematics, or physics.
  • •Experience working with ASIC, SOC, FPGA, RFIC, or MMIC.
  • •Experience contributing to analog or digital CMOS integrated circuit design and/or physical design.
  • •Experience with SystemVerilog, Verilog, VHDL, and/or C/C++ and scripting (e.g., Python) for automation.
Skills:Hands-onSelf-starterExecutionCollaboration
Tech Stack:ASICSOCFPGARFICMMICSystemVerilogVerilogVHDLC/C++PythonMATLABRTLDSPADSSpectreHFSSMomentumSiGeCMOS

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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