Lead Design Engineer
Pune, Bengaluru, Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["Teamwork","Mentoring","Communication","Verilog","SystemVerilog","Python","Perl","Tcl","Unix shell","C"]Lead Design Engineer opportunity in Cadence Tensilica CPU/DSP teams across Pune, Bangalore and Noida. Roles include RTL implementation of Xtensa microprocessor cores or verification of cores/sub-systems, with collaboration across RTL design, design verification and EDA teams. Requires 4+ years in design or design verification, strong digital design fundamentals, Verilog expertise, scripting knowledge (Python, Perl, Tcl), and embedded software understanding to meet timing, area and power goals.
