SOC Verification with Post Silicon Validation

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Product ManagementExperience: 8-12 yearsEducation: bachelorsSkills: ["Communication","Teamwork","Analytical skills","Problem-solving","Willingness to learn"]

Lead end-to-end SoC verification from planning through tape-out, bridging pre-silicon verification with post-silicon validation for server SoC infrastructure. Architect and execute power-aware verification (UPF/CPF, low-power states, PMU, DVFS, clock/reset sequencing) and validate complex debug/trace architectures such as JTAG and ARM CoreSight. Build hybrid C-based and UVM verification environments, drive coverage closure (functional, code, assertions, scenarios), and collaborate with architecture, RTL, firmware, and lab teams for rapid root-cause analysis.

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FursaFursa
AMD
AMD
6 days ago

SOC Verification with Post Silicon Validation

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Source: Company careers pageValidated by: Fursa AI
Last checked: 53 minutes agoStatus: Live

Job Summary

Lead end-to-end SoC verification from planning through tape-out, bridging pre-silicon verification with post-silicon validation for server SoC infrastructure. Architect and execute power-aware verification (UPF/CPF, low-power states, PMU, DVFS, clock/reset sequencing) and validate complex debug/trace architectures such as JTAG and ARM CoreSight. Build hybrid C-based and UVM verification environments, drive coverage closure (functional, code, assertions, scenarios), and collaborate with architecture, RTL, firmware, and lab teams for rapid root-cause analysis.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Product Management
Seniority: Mid level

Key Responsibilities

  • •Architect and execute power-aware verification strategies, validating low-power states, PMU behavior, DVFS, and clock/reset sequencing using UPF/CPF-based simulations.
  • •Own verification of SoC debug and trace infrastructure, including JTAG, hardware triggers, breakpoints, and trace networks such as ARM CoreSight.
  • •Develop and maintain hybrid verification environments using SystemVerilog/UVM and C/C++ direct environments for system-level use-case verification.
  • •Align pre-silicon tests with post-silicon outcomes by authoring portable test content and collaborating with lab teams to mirror post-silicon failures for root-cause analysis.
  • •Drive coverage closure and sign-off, including functional, code, assertion (SVA), and scenario-based coverage to meet tape-out criteria.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8–12 years of hands-on experience in ASIC/SoC design verification with successful tape-out histories.
  • •Strong low-power verification expertise, including static/dynamic low-power concepts, UPF/CPF, and gate-level power-aware simulations (PAGLS).
  • •Deep knowledge of debug and trace infrastructure, including JTAG, IEEE 1149.x, and processor debug architectures (e.g., ARM, RISC-V, x86).
  • •Proficiency with SystemVerilog and UVM, including SystemVerilog Assertions (SVA), plus assembly or C/C++ for SoC bring-up and system-level use cases.
  • •Familiarity with SoC infrastructure and high-speed fabrics, including AMBA protocols (AXI/AHB/APB/CHI), memory controllers, and interrupt controllers.
Experience:8-12 yearsASIC/SoC design verificationTape-outLow-power verificationDebug/trace verification
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationTeamworkAnalytical skillsProblem-solvingWillingness to learn
Languages:English
Tech Stack:SystemVerilogUVMSystemVerilog Assertions (SVA)C/C++AssemblyUPFCPFGate-Level Power-Aware Simulations (PAGLS)DVFSJTAGIEEE 1149.xARM CoreSightAMBAAXIAHBAPBCHI

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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