DFT- SCAN/ATPG

AMD
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Collaboration","Problem-solving","Debug skills","Scripting skills"]

Join AMD’s CDFX team to lead and implement DFX/DFT features for next-generation silicon. Own the DFX design architecture and develop capabilities including SCAN, ATPG, MBIST, and BSCAN, collaborating with DFX architecture, IP, RTL, verification, and PD teams. Develop correct-by-construction DFX designs, support verification, and ensure proper DFT implementation in Scan/ATPG, using strong EDA, scripting, and debug skills.

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FursaFursa
AMD
AMD
1 month ago

DFT- SCAN/ATPG

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Join AMD’s CDFX team to lead and implement DFX/DFT features for next-generation silicon. Own the DFX design architecture and develop capabilities including SCAN, ATPG, MBIST, and BSCAN, collaborating with DFX architecture, IP, RTL, verification, and PD teams. Develop correct-by-construction DFX designs, support verification, and ensure proper DFT implementation in Scan/ATPG, using strong EDA, scripting, and debug skills.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Own/lead DFX design architecting and development of DFX features including SCAN, ATPG, MBIST, BSCAN.
  • •Work with DFX architecture and IP design teams to define DFX requirements and implement DFX designs; support DFX verification.
  • •Collaborate with RTL designers, verification engineers, and the PD team to accelerate identification of functional defects.
  • •Partner with the synthesis and PD teams to ensure correct DFT implementation in Scan/ATPG.
  • •Implement and deploy automated design flows for DFT features in complex SoC ASIC designs or IP subsystems, including end-to-end DFX flow development.

Key Requirements

  • •Experience and understanding of ASIC DFX, including scan synthesis and integration flows.
  • •Experience with ATPG at tile and SoC level, including scan hardware compression, failure mechanisms, and debug processes.
  • •Familiarity with ICI extraction, SSN, IJTAG, EDT, TestKompress, and simulation/verification flows for complex SoCs.
  • •Experience developing and deploying automated design flows for end-to-end DFX/DFT feature creation, including DC/AC scan at-speed development, debug, and test.
  • •Bachelors or Masters degree in computer engineering or electrical engineering; strong EDA/tools and scripting experience (Perl, Python, or TCL) is required.
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CommunicationCollaborationProblem-solvingDebug skillsScripting skills
Tech Stack:ASIC DFXSCANATPGMBISTBSCANDFTScan synthesisFusion CompilerDesign CompilerSpyglassTessentTestKompressSSNIJTAGEDTICl ExtractionLintStatic timing analysisTiming closureRTL

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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