Intel

3 weeks ago

Senior Staff Collateral Design and DFM Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 59 minutes agoStatus: Live

Job Summary

Drive design-for-manufacturability (DFM) methodologies across Intel Foundry’s high-volume manufacturing and advanced logic technology ramps. Lead cross-functional teams spanning process integration, yield, design, OPC/RET, design rules, DTP, and CAD to define DFM rules, translate silicon learning into layout/DTCO updates, and build yield tools and flows. Own scribe line layout and design rule validation/waivers while serving as the technical bridge and supporting foundry customers across market segments.

Location: Santa Clara, Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Lead cross-functional teams to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodes.
•Translate silicon learning and yield insights into actionable feedback for design teams, updating layout and DTCO methodologies/flows to catch yield issues earlier.
•Develop, refine, and optimize yield tools and flows to support inline yield detection and continuous process optimization.
•Define and evolve DFM methodologies by understanding silicon process flows, predicting layout/design marginalities, and developing mitigation rules.
•Manage design rule development, validation, and waiver processes, and serve as the key technical interface between Process Integration, Yield, Device, and Design teams.

Pay and Benefits

Salary: USD 161,550 - 317,600 annually

Perks:Health InsuranceRetirementPaid Leave

Key Requirements

•Master’s in Electrical Engineering, Physics, or a closely related field.
•6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
•Experience with DTCO methodologies, including SRAM and Standard Cell design.
•Experience leading cross-functional teams defining derivative architectures encompassing design rules, transistors, and interconnects.
•Hands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD).

Experience:6+ yearsSemiconductor foundryAdvanced technology development

Education:Master's in Electrical Engineering, Physics (or closely related field)

Skills:CommunicationCollaborationCross-functional leadershipPrioritizationProject management

Tech Stack:DFMDTCOSRAMStandard CellDesign rulesTransistorsInterconnectsCADOPC/RETDTPYield toolsInline yield detectionProcess optimizationDRCVerificationTest chip designScribe line optimizationFinFETGAA FETBackside Power Delivery (BSPD)

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

3 weeks ago

Senior Staff Collateral Design and DFM Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 59 minutes agoStatus: Live

Job Summary

Location: Santa Clara, Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Lead cross-functional teams to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodes.
•Translate silicon learning and yield insights into actionable feedback for design teams, updating layout and DTCO methodologies/flows to catch yield issues earlier.
•Develop, refine, and optimize yield tools and flows to support inline yield detection and continuous process optimization.
•Define and evolve DFM methodologies by understanding silicon process flows, predicting layout/design marginalities, and developing mitigation rules.
•Manage design rule development, validation, and waiver processes, and serve as the key technical interface between Process Integration, Yield, Device, and Design teams.

Pay and Benefits

Salary: USD 161,550 - 317,600 annually

Perks:Health InsuranceRetirementPaid Leave

Key Requirements

•Master’s in Electrical Engineering, Physics, or a closely related field.
•6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
•Experience with DTCO methodologies, including SRAM and Standard Cell design.
•Experience leading cross-functional teams defining derivative architectures encompassing design rules, transistors, and interconnects.
•Hands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD).

Experience:6+ yearsSemiconductor foundryAdvanced technology development

Education:Master's in Electrical Engineering, Physics (or closely related field)

Skills:CommunicationCollaborationCross-functional leadershipPrioritizationProject management

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor