Principal Digital Design Engineer / Chip Lead

Micron Technology
Boise, San Jose
Workplace: OnsiteFull timeUSD 178,000 - 389,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsSkills: ["Technical leadership","Decision-making","Written communication"]

Own chip-level digital design leadership for Micron’s Interface Pathfinding team, bridging architecture through RTL, synthesis, timing closure, and tape-out. Drive SystemVerilog RTL for control/CSR blocks, define SDC and CDC strategies, and coordinate verification with DV teams using coverage, assertions, formal and constrained-random methods. Manage mixed hard/soft IP integration and author technical specifications that accelerate follow-on PHY development.

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Micron Technology
Micron Technology
1 week ago

Principal Digital Design Engineer / Chip Lead

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Job Summary

Own chip-level digital design leadership for Micron’s Interface Pathfinding team, bridging architecture through RTL, synthesis, timing closure, and tape-out. Drive SystemVerilog RTL for control/CSR blocks, define SDC and CDC strategies, and coordinate verification with DV teams using coverage, assertions, formal and constrained-random methods. Manage mixed hard/soft IP integration and author technical specifications that accelerate follow-on PHY development.
Location: Boise, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define top-level chip architecture and partition responsibilities across hard and soft IP blocks, owning integration with third-party soft IP.
  • •Author, review, and maintain synthesizable RTL (SystemVerilog) for soft IP control blocks, CSR/register file, clocking control logic, and top-level integration.
  • •Develop and own chip-level timing constraints (SDC), including clock domain crossing strategy and timing budgets per block for physical design.
  • •Drive synthesis (DC/Genus) and guide optimization for PPA targets across all design blocks.
  • •Coordinate verification with DV staff using assertion-based verification, coverage-driven verification, formal methods, and constrained-random techniques.

Pay and Benefits

Salary: USD 178,000 - 389,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVisionPaid LeavePaid Time-off

Key Requirements

  • •BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
  • •10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead/design lead/senior designer role.
  • •Expert proficiency in SystemVerilog RTL design and coding best practices.
  • •Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus).
  • •Experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment.
Experience:10+ yearsASICSemiconductorPHYMixed-signal
Education:
Skills:Technical leadershipDecision-makingWritten communication
Tech Stack:SystemVerilogRTLASICDCGenusPrimeTimeTempusVCSXceliumVerdiDVESDCCDCSpyGlassJasperGoldFormal methodsConstrained-randomAssertion-based verificationSystemVerilog RTLI2C

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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