Memory Package Integration Architect

Micron Technology
Boise, San Jose
Workplace: OnsiteFull timeUSD 143,000 - 398,000 annuallyFunction: Software EngineeringExperience: 6+ yearsEducation: mastersSkills: ["Cross-stack collaboration","Technical leadership","Customer-facing partnership","Strategic planning","Problem-solving"]

Define next-generation packaging pathfinding and system architectures for complex memory systems, optimizing for speed, bandwidth, power, capacity, thermal, mechanical, and electrical performance. Lead cross-stack co-optimization across silicon, package, board, and system, and drive long-term packaging strategy that influences industry standards. Partner with internal teams, customers, and senior leaders to turn end-to-end memory architecture knowledge into scalable products, including AI-based multi-physics efficiency solutions.

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FursaFursa
Micron Technology
Micron Technology
1 week ago

Memory Package Integration Architect

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Define next-generation packaging pathfinding and system architectures for complex memory systems, optimizing for speed, bandwidth, power, capacity, thermal, mechanical, and electrical performance. Lead cross-stack co-optimization across silicon, package, board, and system, and drive long-term packaging strategy that influences industry standards. Partner with internal teams, customers, and senior leaders to turn end-to-end memory architecture knowledge into scalable products, including AI-based multi-physics efficiency solutions.
Location: Boise, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Define next-generation package pathfinding and system architectures optimizing for speed, bandwidth, power, capacity, thermal, mechanical, and electrical performance.
  • •Lead cross-stack co-optimization across silicon, package, board, and system using a package-centric solutions approach.
  • •Drive long-term memory technology packaging strategy and influence industry standards.
  • •Partner with silicon, system design teams, and customers to deliver next-generation and disruptive solutions for edge-AI and datacenter memory products.
  • •Develop AI-based multi-physics solutions to improve engineering efficiency.

Pay and Benefits

Salary: USD 143,000 - 398,000 annually
Perks:Paid LeaveLearning BudgetWellness StipendHealth InsuranceParental LeavePaid HolidaysEquityRecognition

Key Requirements

  • •Master’s degree (or equivalent practical experience) in EE, CE, CS, or a related field.
  • •6+ years of extensive hands-on experience in memory systems package design, including signaling, IO design, and PDN design.
  • •Deep understanding of memory timing, signaling, power, and package process technology.
  • •Working knowledge of EDA tools for design, analysis, and simulation of electronic packaging (Cadence, Siemens, Ansys).
  • •Experience applying AI or LLMs for engineering efficiency.
Experience:6+ yearsMemory systemsSemiconductorElectronic packaging
Education:Master's
Skills:Cross-stack collaborationTechnical leadershipCustomer-facing partnershipStrategic planningProblem-solving
Tech Stack:CadenceSiemensAnsysEDA toolsAILLMsMulti-physicsSignal integrityPower integrityPDNSignalingIO designThermal analysis

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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