Lead Software Engineer - Logic Synthesis

Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 3-5 yearsEducation: mastersSkills: ["Communication","Attention to details","Collaboration","Ability to work in multi-site projects"]

Develop and maintain the Palladium synthesizer, implementing new VHDL/Verilog feature support and driving logic optimization to improve synthesizer performance. Work on RTL modeling and verification-oriented capabilities, including BFMs and exposure to UVM and SC/TLM methodologies. Partner with multi-site teams and use strong software engineering fundamentals in C/C++ and operating system concepts to deliver high-quality EDA/CAD functionality.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
1 day ago

Lead Software Engineer - Logic Synthesis

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Develop and maintain the Palladium synthesizer, implementing new VHDL/Verilog feature support and driving logic optimization to improve synthesizer performance. Work on RTL modeling and verification-oriented capabilities, including BFMs and exposure to UVM and SC/TLM methodologies. Partner with multi-site teams and use strong software engineering fundamentals in C/C++ and operating system concepts to deliver high-quality EDA/CAD functionality.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Develop and maintain the synthesizer for Palladium.
  • •Implement new VHDL/Verilog feature support in the synthesizer.
  • •Perform logic optimization to improve synthesizer performance.
  • •Support RTL modeling and related verification-oriented workflows.
  • •Collaborate with multi-site teams on multi-person projects.

Key Requirements

  • •Bachelor or Master's degree in EE/CS/CE with 3–5 years of industry experience.
  • •Proficient with C/C++ and operating system concepts.
  • •Experience with design modeling using Verilog/SV, VHDL, or SysC.
  • •Knowledge of RTL modeling of BFMs and exposure to verification methodologies using UVM and SC/TLM.
  • •EDA/CAD tool development or logic design verification experience; AI tool experience (Copilot/Claude code) is preferred.
Experience:3-5 yearsEDALogic synthesisRTL modelingVerificationSemiconductor
Education:Master's in EE/CS/CE
Skills:CommunicationAttention to detailsCollaborationAbility to work in multi-site projects
Tech Stack:C/C++Operating systemsVerilogSystemVerilog (SV)VHDLSysCRTL modelingBFMUVMSC/TLMEDA/CAD toolsCopilotClaude code

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor