New College Grad - Engineer, ASIC Digital Design
Minneapolis
Workplace: OnsiteFull timeUSD 86,000 - 146,000 annuallyFunction: Design (Product/UX/UI/Visual)0Education: bachelorsSkills: ["Written and verbal communication","Collaboration","Ability to learn quickly","Problem-solving"]Design and develop RTL for next-generation DRAM memory controllers and subsystems, using SystemVerilog. Collaborate with analog, verification, physical design, and validation teams to deliver production-ready silicon. Create and validate HDL models, support simulation and co-simulation, and analyze performance. Participate in chip bring-up, debugging, and validation, while using scripting, automation, and AI-enabled tools to improve design workflows and productivity.
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